Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
1998-09-28
2001-02-13
Lefkowitz, Sumati (Department: 2781)
Electrical computers and digital data processing systems: input/
Interrupt processing
C709S241000
Reexamination Certificate
active
06189065
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to data processing systems and in particular to data processing systems utilizing multiple superscalar processors. More particularly, the present invention relates to an interrupt source controller and assignment of interrupts to multiple superscalar processors utilized by the data processing system.
2. Description of the Related Art
An interrupt is an independent signal generated anywhere in a data processing system and is a notification to the processor of the occurrence of an event. External interrupts are usually generated by devices or sub-systems connected to the data processing system. In the case of external interrupts, a signal may be generated by striking a key on the keyboard, depressing a mouse button or a signal from the printer that the printer is active. The interrupt generally has no correlation with the execution of a program, because it originates outside the program. It may occur at any time during the execution of instructions, but is latched inside the processor to be addressed when the active instruction finishes execution. The occurrence of an interrupt is a significant event in the operation of a modern, high speed processor.
Much of the processor's ability to execute at maximum speed comes from the fact that the processor may predict what it will have to do next. This prediction capability is based on the processor's recent past operations. When an interrupt is taken by the processor, the operational context is changed and much of the data used to make operational predictions may become invalid. This may significantly slow down the processor.
Interrupts are usually maskable or non-maskable. Maskable interrupts may be suppressed by an interrupt flag that is placed in the status register referencing a particular interrupt or group of interrupts. However, non-maskable interrupts are typically priority interrupts that must be serviced immediately.
Data processing systems utilizing multiple superscalar processors have a significantly higher interrupt rate than prior art systems. Prior art interrupt source controllers distribute interrupts to the processors in a multiple processor system utilizing one of the following methods: randomly assign interrupts to one of the processors, assign the interrupt to one specific processor or notify all processors in the system.
Randomly assigning an interrupt to any one of the multiple processors provides a uniform probability of finding a processor without accumulated interrupt data. The lack of consistent and predictable interrupt data on all the processors restricts the efficiency of the random assignment method.
Assigning interrupts to one specific processor insures the best probability of that processor being able to accurately predict operations in the interrupt context. However, as the interrupt load increases, the single processor method may become a bottleneck in the system and load balancing becomes a problem.
Assigning the interrupt to all processors maximally disrupts the system. All processors are interrupted and it must be determined which processor will actually proceed to service the interrupt condition.
In reality, software in these systems mask off interrupts in most processors so that they effectively work as systems in which the interrupts are directed to only one processor with the associated load balance problems. As should thus be apparent, it would be desirable to provide a method that would allow an interrupt source controller in a multiple processor data processing system to service external interrupts promptly, provide a relatively predictable interrupt assignment scheme and improve interrupt load balancing.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide a method and system that will assign external interrupts to one of multiple superscalar processors, in a data processing system, in a relatively predictable manner.
It is another object of the present invention to provide a method and system that will assign multiple external interrupts to succeeding superscalar processors, in a multiple processor data processing system, as each processor reaches a pre-determined interrupt load.
It is a further object of the present invention to provide a method and system that will improve load balancing of the interrupts between processors.
It is yet another object of the present invention to provide a method and system that will direct interrupts to more than one processor.
It is a further object of the present invention to provide a method and system that will offload interrupts from a given processor as a limit is reached.
The foregoing objects are achieved as is now described.
Interrupts from an I/O subsystem are first directed to a first processor in a multiple superscalar processor data processing system. If an interrupt load on the processor is sufficiently high, the interrupt is sent (offloaded) to a second pre-determined processor. The process continues throughout all superscalar processors in the system and each processor builds interrupt prediction data corresponding to the interrupt load on the individual processor. A threshold counter may be added to the logic so offloading does not take place until a specified number of interrupts are queued within that specific processor, thus providing a pre-determined level of prediction data. Some processors may be left out of the offload string so they are not disturbed by an interrupt.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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Arndt Richard Louis
Chen Wen-Tzer Thomas
Felsman Bradley Vaden Gunter & Dillon, LLP
International Business Machines - Corporation
Leeuwen Leslie A. Van
Lefkowitz Sumati
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