Surface mount semiconductor package, die-leadframe...

Details Surface mount semiconductor package, die-leadframe... Surface mount semiconductor package, die-leadframe...

1999-05-27

2001-10-23

Gaffin, Jeffrey (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S820000, C361S760000, C361S764000, C257S666000, C257S668000, C257S669000, C257S670000, C257S676000, C174S050510, C174S260000, C174S261000

Reexamination Certificate

active

06307755

ABSTRACT:

BACKGROUND OF THE INVENTION
Semiconductor devices in the form of integrated circuit chips (ICs) must typically be mounted on a flat surface such as a printed circuit board when they are incorporated into a product such as a computer or cellular phone. No surface-mount semiconductor packaging technology exists today that is capable of meeting the needs of the next-generation of discrete power semiconductor devices and Ics.
Such surface-mount power packages should include at least the following features:
1. A low electrical resistance.
2. The capability of shunting current and reducing the lateral resistance in a device's metal interconnect.
3. A low thermal resistance.
4. The capability of achieving high currents vertically (through backside) or laterally (topside).
5. High manufacturability.
6. A low intrinsic material cost.
7. A low manufacturing cost.
8. Reliable operation in power applications.
9. The ability to acilitate at least three (and preferably more) isolated connections to the semiconductor.
10. A low profile (height) and small footprint.
Power semiconductor devices and ICs come in two types, those that conduct high currents because they exhibit low on-state voltage drops (and hence low power dissipation) and those that conduct “high” currents because they dissipate large amounts of power. Because of the varied use, construction, and operation of such power devices, the first two features listed (i.e. low electrical resistance) can be achieved in lieu of the third feature (low thermal resistance), but ideally one package should offer both low electrical and thermal resistance.
The fourth feature, a high current flow laterally or vertically, specifies that a power package should ideally be applicable to both lateral and vertical power devices, but at least one of the two orientations should be high current capable.
Of course, the package must be highly manufacturable since power transistors are used in high quantities, billions of units yearly, worldwide. Any a intrinsic manufacturing repeatability or yield problem would have dire consequences for the supplier and likely the user of such devices.
Another feature is low cost, including the package material cost and the cost of its manufacture. Of these, the material cost is fundamental since the price of certain materials such as gold wire, plastic molding, copper leadframes, etc., are based on the world market for the raw material and cannot be substantially changed through simple increases in semiconductor product volume. Package designs using smaller amounts of material are inherently cheaper to produce.
The reliability of a package in a power application means it must survive operating conditions commonly encountered in power device use, such as current spikes, higher ambient temperatures than normally encountered, significant self heating, thermal shock from repeated thermal transients, etc. Repeated pulses of current or heating can provoke fatigue-related failures, particularly at metallurgical junctions and interfaces. Fewer interfaces are preferable.
Two terminal packages are needed for diodes, transient suppressors, and fuses, while packages supporting at least 3 connections are useful for discrete transistors. Four connections up to 8 connections are extremely valuable for a variable of smarter power semiconductor components. Beyond 8 distinct connections, the use of such power package technology is concentrated on power integrated circuits.
Low profile surface mount packages, while not universally required, make it convenient for PC board manufacturing since power devices packaged in low profile packages have the same characteristics of other ICs on the same board and hence avoid the need for special handling. In some cases like battery packs, PCMCIA cards and cell phones, the low profile package may be crucial in meeting a critical thickness in the final end product.
Small footprint is generally a matter of overall product size, especially in portable electronics where size is an important consumer buying criteria—the smaller the better.
In a related consideration, the smaller the package footprint is on the board and the larger the semiconductor die it contains, the performance for a given size is greater.
While these goals may seem obvious, the fact is that today's power semiconductor-packaging technology does not meet these needs adequately, cost effectively, and in some cases, at all.
Present Surface Mount Package Approaches
FIG. 1
describes the process flow for the manufacture of a conventional prior-art surface mount package, such as the 8-pin small-outline (SO-8) package originally developed for ICs, or the ubiquitous 3-pin small outline transistor (SOT23) package. The flow starts with one or more semiconductor dice, a metal leadframe, and conductive epoxy or solder to attach the dice to the leadframe in an area known as the die pad. The assembly is then wire-bonded, connecting the metal “posts” of the package to the aluminum bonding pads on the device or IC with gold (or in some cases aluminum) wire. The bonding uses a thermo-compression or ultrasonic technique to achieve a good electrical connection and sufficient mechanical strength to withstand the subsequent manufacturing steps and operating conditions. After wire-bonding, the leadframe, still held together by a series of metal straps or tie-bars, is placed in a mold and subsequently injected with hot liquid plastic, also known as molding compound.
After the plastic cools, it provides mechanical rigidity to the bond wires, the die pad, and the package leads, so that the external leads can be clipped from any tie bars, thereby separating the unit from any others which may have been manufactured on the same tie bar.
Finally the leads are bent into their final shape. The bending process requires “clamping” the leads so that undue mechanical stress is not placed on the plastic package which could lead to cracking of the plastic.
FIG. 2
illustrates the prior art leadframe
10
comprising a repeated cell
11
(with die pad
12
and lead-assembly
13
A and
13
B) repeated 5 to 25 times in a strip. The strip comprises three tie bars that hold the repeated cells together in the strip until later separated after plastic injection molding has occurred. The tie bars comprise two outer tie bars
14
A and
14
C, holding the package leads
15
A and
15
B in place, and an inner tie bar
14
C that holds the die pad
12
secure during the assembly process. The actual number of pins may vary depending on the package, with 3-, 6-, 8-, 14- and 16-pin packages being commonly employed. An end-piece
16
(located on each end) holds the entire strip together during manufacture, by securing tie bars
14
A,
14
B, and
14
C.
FIGS. 3A-3G
illustrate cross sectional views of the steps of the flow described in FIG.
1
.
The leadframe
10
in
FIG. 3A
includes the center die pad, and two of the leads
15
A and
15
B. In
FIG. 3B
, the semiconductor die
17
is attached (using a thin layer of solder or epoxy not shown) to the die pad
12
. The die-attach operation is then followed by wire bonding in FIG.
3
C. For each of the bond wires
18
the ball bond
19
(the first bond performed) is present on the die, and the wedge bond
20
(the last bond for each wire) is present on the lead (also called the post). The wedge bond occurs where the wire is cut. The difference between the shape of the ball bond and the wedge bond is characteristic of the wire bonding machine's operation. The wedge bond is preferred on the leadframe
15
A and
15
B to avoid the risk of damage to the semiconductor from the stress associated with the wire cutting.
In
FIG. 3D
, the plastic
21
is injected (shown by a dotted line) to cover each die
17
and its associated bond wires
18
and leads
15
A,
15
B as shown in the top view of FIG.
3
E. The tie bars
14
A and
14
B are intentionally left uncovered. A portion of tie bar
14
C is covered by the plastic but the most of tie bar
14
C remains uncovered. After trimming, the individual packaged die and its separate leads are held

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