Substantially planar semiconductor topography using...

Details Substantially planar semiconductor topography using... Substantially planar semiconductor topography using...

2000-02-25

2001-12-04

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S692000, C438S695000, C438S781000, C257S759000, C257S760000

Reexamination Certificate

active

06326298

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to an integrated circuit which employs a multilevel interconnect structure. The multilevel interconnect structure includes at least two layers of interconnect spaced from each other by an interlevel dielectric structure. The dielectric structure contains a combination of dielectric layers upon which the upper layer surface can be readily planarized to a substantially uniform. level over regions of both densely spaced and sparsely spaced interconnect.
2. Description of the Relevant Art
The density of active devices placed upon a single monolithic substrate has steadily increased over the years. As the minimum feature size on an integrated circuit decreases, the active device density increases. As a result, the density of overlying interconnect must also be increased. With limited area, interconnect density is often forced to dimensionally expand above the substrate in a multilevel arrangement. Accordingly, multilevel interconnect structures have become a mainstay in modern integrated circuit manufacture.
Loss of topographical planarity occurs from the numerous levels of a multilevel interconnect structure. Non-planarity causes many problems which impact manufacturing yield. Exemplary problems include stringers arising from incomplete etching over severe steps, failure to open vias due to interlevel dielectric thickness disparity, step coverage problems, and depth-of-focus problems. Many manufacturers have undergone extensive work on methods for planarizing layers. Generally speaking, manufacturers have focused upon planarizing the dielectric layers (i.e., the interlevel dielectric surfaces on which subsequent conductive layers are placed) . A planarized dielectric affords more accurate placement of overlying levels of conductors and dielectrics.
One of the more complex problems involved in manufacturing a reliable multilevel interconnect structure is the planarization of the interlevel dielectric layers formed on each level of interconnect. There are typically two types of interlevel dielectrics: a metal interlevel dielectric and a polysilicon interlevel dielectric. The metal interlevel dielectric is formed upon metal interconnect, either the first, second or subsequent layers of metal within the multilevel interconnected structure, and the polysilicon interlevel dielectric is formed upon only polysilicon interconnect, generally the first level of interconnect. Accordingly, a multilevel interconnect structure herein is defined as one incorporating polysilicon interlevel dielectric and one or more metal interlevel dielectrics.
Planarization of an interlevel dielectric, whether metal or polysilicon, is a matter of degree. There are several types of planarization techniques ranging from minimal planarization (i.e., smoothing); intermediate planarization, involving only isolated or local planarization; and extensive planarization, involving global planarization. Smoothing entails merely lessening the step slopes at the dielectric surface while not significantly reducing the disparities in surface elevation. On the other hand, local planarization substantially reduces if not eliminates entirely the disparities in elevation in localized areas across the substrate. Global planarization, however, is designed to eliminate disparities in elevation over the entire topography of the integrated circuit. As one can imagine, global planarization is extremely difficult to achieve on a multilevel interconnect structure having, for example, two or more levels of metal and/or polysilicon interconnect.
Most manufacturers have quantified the level of planarization, and have attributed a planarization factor generally described as total indicated range (“TIR”). If the planarization factor or TIR is large, then subsequent interconnect placed on the interlevel dielectric surface may suffer from numerous problems such as those described above. Even though local planarization is achieved, absent global planarization, many of these problems remain, especially at the junction between the local/global planarization areas.
For example, if a sub-micron interconnect feature is to be patterned, the TIR must be less than approximately 0.5 micron. Absent global planarization, such sub-micron features cannot be readily obtained.
In order to attempt global planarization, conventional planarization processes involved many separate types of planarization. Limited planarization is achieved through a sacrificial etchback technique. Sacrificial etchback involves depositing a sacrificial layer across the interlevel dielectric topography, and then removing a sacrificial layer at the same etch rate as the underlying dielectric. The sacrificial etchback technique is well documented, and is generally valid only for the planarization of dielectric topographies in which the underlying features are 2.0 to 10.0 microns apart. For large regions between trenches, the step height will not be reduced, since the thickness of the sacrificial material on top of such features will be the same as the thickness over the adjacent trench. Another planarization technique involves deposition of a planarization layer, followed by etchback, followed by another deposition. Thus, an oxide can be deposited on etched and then additional oxide can be placed in a deposit-etch-deposit sequence, all of which can be repeated as necessary. One problem involving deposit-etch-deposit is the very low throughput involved in depositing, etching and then re-depositing within, e.g., a CVD/etch tool.
A more recent planarization process called chemical-mechanical polishing (“CMP”), overcomes to some extent the limitations of sacrificial etchback and block masking. CMP involves application of a slurry and abrasive pad across the entire topography. CMP forces planarization of that topography commensurate with the planarity of the pad surface. Provided the pad surface is relatively flat, the surface would be translated to the interlevel dielectric surface. Unfortunately, however, when force is applied to the pad, the pad will conform or flex to the unevenness of the topography on which it is applied. Thus, while high elevational areas (or peaks) receives substantial polishing, low elevational areas (or valleys) are also slightly abraded and removed.
Planarization can become quite difficult in regions in which there are relatively large distances between devices on the semiconductor surface (sparse regions). Conductors separated by a relatively large distance present an especially difficult problem for planarization because the large spacing contributes to a disparity in height along the surface topography. Such a disparity contributes to greater flexing of a CMP pad; this greater flexing decreases the amount of planarization possible because the topography of the surface being polished mimics the orientation and topography of the pad itself.
It is desirable to formulate a planarization technique which can achieve substantial global planarization of the entire upper surface of an interlevel dielectric. Global planarization, presented as small TIR, may be achieved through CMP but with a preconditioning of the surface upon which the polishing pad is placed. If the surface, in its initial state, is relatively smooth and planar, then the CMP pad will not flex to a substantial degree. Such minimizing of flexing aids in the degree of planarization achieved. If the topography of the underlying surface mimics the topography and orientation of the pad, minimum flexing of the pad corresponds to a minimum disparity in elevation of the underlying interlevel dielectric surface. Minimizing disparities in elevation and thus minimizing the flexure of the CMP pad is thereby a desired outcome of a to-be-planarized interlevel dielectric surface. If a surface can maintain these properties, the CMP will be more effective as a planarization tool.
It would be desirable to derive a planarizing layer, layers, or structures which could be deposited upon a layer of

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