Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-13
2001-11-27
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000
Reexamination Certificate
active
06323518
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an insulated gate type semiconductor device having a protection element, and a method of manufacturing the device. Especially, the invention relates to an insulated gate semiconductor device which is suitable for forming a trench type insulated gate semiconductor element with a lateral type insulated gate semiconductor element or a polycrystalline silicon diode concerning an operation of the trench type insulated gate semiconductor element of in an identical chip, and a method of manufacturing the device.
For example, power MOSFET(Metal Oxide Semiconductor Field Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor) are known as insulated gate type semiconductor elements. For improving a reliability and an added -value of the power MOSFET and the IGBT and for reducing a cost and a size of these semiconductor elements, in a case of forming these elements of power devices in a semiconductor substrate, an insulated gate type semiconductor device having a protection element such as a MOSFET with the power MOSFET and the IGBT in an identical chip is proposed. For example, a temperature detection circuit with a lateral type MOSFET and a polycrystalline silicon diode is formed in a drain region of a power MOSFET, using the manufacturing process of the planar type power MOSFET, as described in the Japanese Patent laid-open No. 63-229758. The temperature detection circuit turns off the power MOSFET, when the temperature of semiconductor chip is overheated over a pre-determined temperature.
The Japanese Patent laid-open discloses a polycrystalline silicon diode for preventing an electrostatic destruction between a gate and a source of a planar type power MOSFET in a chip of the planar type power MOSFET.
The trench type power MOSFET is proposed as an insulated gate type semiconductor element different from the planar type power MOSFET. In the trench type power MOSFET, a groove (trench) is formed in a semiconductor layer, and then a gate layer is formed in the groove through a gate oxide film, for reducing a power loss of the element. In addition, a channel width per unit area is lengthened by forming a channel in a side surface of the groove. In producing the trench type power MOSFET, a method of forming the groove after forming a source diffusion layer and a body (channel) diffusion layer is proposed, as described in the U.S. Pat. No. 5,298,442. On the other hand, a method of forming the source diffusion layer and the body (channel) diffusion layer after forming the groove is proposed, as described in Japanese Patent laid-open No. 4-17371. The former of these method is mainly adopted in general.
A method of forming the trench type power MOSFET and a FET protecting the power MOSFET on an identical chip is studied in Japanese Patent laid-open No. 9-82954. As the result, the method of using a gate buried in the trench as a gate of the FET protecting the trench type power MOSFET is proposed.
SUMMARY OF THE INVENTION
A method of forming a trench type power MOSFET and a FET protecting the trench type power MOSFET in an identical chip is disclosed in Japanese Patent laid-open No. 9-82954. In the laid-open, a general manufacturing method of forming a source diffusion layer of the trench type power MOSFET before forming the groove is used. Since a lateral type MOSFET using a side surface of the groove-gate buried in the trench is used for a protection circuit, the source region of the lateral MOSFET is formed simultaneously with the source region of the trench type power MOSFET. Therefore, it is advantageous that the mask for forming the source diffusion layer of the lateral type MOSFET for the protection circuit is unnecessary. However, it is a problem that the element area increases to lengthen the gate width W, because only a part of the side surface of the groove-gate buried in the trench is used as the gate of the lateral type MOSFET for the protection circuit. In addition, it is another problem that a gate-to-source capacitance increases, because the body region, which is formed in a bottom of the groove-gate through a gate oxide film, is connected to the source.
A general manufacturing method of forming a source diffusion layer of a trench type power MOSFET before forming a groove is disclosed in the U.S. Pat. No. 5,298,442. In applying the manufacturing method of the built-in of a conventional lateral MOSFET having a source diffusion layer and a drain diffusion layer in self-alignment to a gate as disclosed in Japanese Patent laid-open No. 63-229758, a mask for forming the source diffusion layer of the lateral type MOSFET is necessary. Therefore, it is a problem that the manufacturing cost rises. In addition, the source diffusion layer of the trench type power MOSFET and the source diffusion layer of the lateral MOSFET are formed before forming the groove. Therefore, there is a problem that it is difficult to make shallow the source diffusion layer and the channel diffusion layer of the trench type power MOSFET and the source diffusion layer of the lateral type MOSFET, because of a process, which is generally applied for forming a groove, of forming a sacrifice oxide film in high temperature and long time. Therefore, it is a problem that reduction of gate-to-source capacitance of the trench type power MOSFET, reduction of power loss with shortening channel-length, and reduction of gate-to-source capacitance of the lateral type MOSFET are difficult.
On the other hand, in regard to a method of forming a trench type power MOSFET with a diode protecting a gate of the power MOSFET from an electrostatic destruction in an identical chip, study for reducing masks to the utmost with considering power loss reduction of the power MOSFET and prevention of increase of the gate-to-source capacitance of the power MOSFET is not sufficient.
An object of the invention is to present an insulated gate type semiconductor device in which improving a performance is possible, even if a trench type insulated gate semiconductor element is formed with a lateral insulated gate semiconductor element or a polycrystalline silicon diode in an identical chip.
Another object of the invention is to present a method of manufacturing an insulated gate type semiconductor device in which reducing process steps in forming a trench type insulated gate semiconductor element with a lateral type insulated gate semiconductor element or a polycrystalline silicon diode in an identical chip is possible.
For achieving the object, an insulated gate type semiconductor device according to the invention has a trench type insulated gate semiconductor element, and a lateral type insulated gate semiconductor element concerning an operation of the trench type insulated gate semiconductor element. In a main surface of a semiconductor layer on a semiconductor substrate in the trench type insulated gate semiconductor element, a plurality of grooves are provided. In the grooves, gate layers connected to a first electrode are provided through gate insulating films. In a surface opposite to the main surface of the semiconductor layer, a second electrode is provided. A diffusion layer connected to a third electrode is provided between gate layers. A main gate layer connected to a gate electrode in the main surface of a semiconductor layer on the semiconductor substrate of the lateral type insulated gate semiconductor element is provided through a gate insulating film. In regions of the semiconductor layer between which a region facing the main gate layer is put, a drain diffusion layer connected to a drain electrode and a source diffusion layer connected to a source electrode are provided. A depth of the diffusion layer connected to the third electrode is not greater than a depth of the source diffusion layer in the lateral type insulated gate semiconductor element.
In constituting the aforementioned insulated gate type semiconductor device, it is possible to add following elements.
(1) The gate insulating film of the trench type insulated gate semiconductor element is formed in t
Nakazawa Yoshito
Sakamoto Kozo
Yanokura Eiji
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Meier Stephen D.
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