Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-04-27
2001-10-09
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S672000
Reexamination Certificate
active
06300242
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having multilayer wiring or interconnects and to a method of fabricating the same.
To provide a semiconductor LSI device operable at a higher speed with improved reliability, there has been developed a technique for forming an interconnect using copper (Cu) having lower resistance than aluminum (Al) that has been used conventionally for interconnect formation.
To miniaturize the semiconductor LSI device, the number of layers contained in a multilayer wiring or interconnect structure has been increased gradually.
Referring now to
FIG. 16
showing a cross-sectional structure of a conventional semiconductor device, a description will be given to a method of forming, by using a dual damascene method (Dual Damascene: A ULSI WIRING TECHNOLOGY, C. W. Kannta et. al. Jun. 11-12 1991, VMIC Conference), an upper interconnect to be connected to a lower interconnect through a via contact above a semiconductor substrate formed with the lower interconnect.
First, a first interconnect groove
3
is formed in a first interlayer insulating film
2
on a semiconductor substrate
1
. Then, a lower interconnect
7
composed of a first adhesion layer
4
, a first seed layer
5
, and a first copper plating layer
6
is formed in the first interconnect groove
3
.
Next, a second interlayer insulating film
8
is deposited, masked with a mask pattern (not shown) formed on the second interlayer insulating film
8
, and subjected to dry etching for successively forming a via hole
9
and a second interconnect groove
10
in the second interlayer insulating film
8
. Thereafter, a second adhesion layer
11
and a second seed layer
12
composed of a copper film are deposited successively on the second interlayer insulating film
8
including the inner surfaces of the via hole
9
and the second interconnect groove
10
.
Next, a second copper plating layer
13
is deposited on the second seed layer
12
by electroplating using the second seed layer
12
as a cathode for plating. Then, the portions of the second adhesion layer
11
, the second seed layer
12
, and the second copper plating layer
13
exposed on the second interlayer insulating film
8
are removed such that a via contact
14
and an upper interconnect
15
each composed of the second adhesion layer
11
, the second seed layer
12
, and the second copper plating layer
13
are formed.
With the increasing miniaturization of the semiconductor LSI device, however, the following problems are encountered by the conventional method of forming multilayer wiring or interconnects.
(1) Since the mask pattern for forming the via hole is inevitably displaced from the lower interconnect
7
, the via contact
14
is also displaced from the lower interconnect
7
. Consequently, the contact area between the lower interconnect
7
and the via contact
14
decreases and a faulty connection occurs between the lower interconnect
7
and the via contact
14
.
FIG. 16
shows the case where the via contact
14
is displaced from the lower interconnect
7
by the displacement size b.
(2) If he via hole
9
has a high aspect ratio, the top portion of the via hole
9
is clogged with the second copper plating layer
13
before the inner portion of the via hole
9
is filled with the second copper plating layer
13
, since the speed at which the second copper plating layer
13
grows adjacent the top portion of the via hole
9
is higher than the speed at which the second copper plating layer
13
grows adjacent the bottom of the via hole
9
during the formation of the second copper plating layer
13
by electroplating. As a result, a void is produced within the via hole
9
to cause a faulty connection between the lower interconnect
7
and the upper interconnect
15
.
SUMMARY OF THE INVENTION
In view of the foregoing, it is therefore an object of the present invention to prevent a reduction in the contact area between the lower interconnect and the via contact even if a mask pattern is displaced and prevent a void from being produced within the via hole during the formation of the via contact.
To attain the object, a first method of fabricating a semiconductor device according to the present invention comprises: a first step of depositing a first metal film on an insulating film on a semiconductor substrate; a second step of depositing a first interlayer insulating film on the first metal film; a third step of forming, on the first interlayer insulating film, a first mask pattern having an opening over a region in which a via hole is to be formed, etching the first interlayer insulating film by using the first mask pattern as a mask, and thereby forming a via hole in the first interlayer insulating film; a fourth step of growing a second metal film in the via hole to form a via contact composed of the second metal film and forming a recessed portion over the via contact in the via hole; a fifth step of forming, in the recessed portion, a cap layer composed of a material different from a material composing the first metal film; a sixth step of forming, on the first interlayer insulating film, a second mask pattern covering a region in which a lower interconnect is to be formed, etching the first interlayer insulating film by using the second mask pattern and the cap layer as a mask, and thereby patterning the first interlayer insulating film; a seventh step of etching the first metal film by using the cap layer and the patterned first interlayer insulating film as a mask and thereby forming a lower interconnect composed of the first metal film; an eighth step of depositing a second interlayer insulating film over an entire surface of the semiconductor substrate; a ninth step of planarizing the second interlayer insulating film and exposing the via contact or the cap layer; and a tenth step of forming, on the second interlayer insulating film, an upper interconnect to be connected to the via contact or the cap layer.
In accordance with the first method of fabricating a semiconductor device, the lower interconnect is formed by forming the cap layer composed of the material different from the material composing the first metal film such that the top surface of the via contact is covered therewith and patterning the first metal film by using the mask pattern for forming the lower interconnect and the cap layer as a mask. This ensures the formation of the lower interconnect over the entire bottom surface of the via contact covered with the cap layer even if the mask pattern for forming the lower interconnect is displaced and thereby prevents a reduction in the contact area between the lower interconnect and the via contact.
Since the first method of fabricating a semiconductor device grows the second metal film on the region of the first metal film composing the lower interconnect which is exposed in the via hole, the second metal film can be grown only from the bottom side of the via hole. This prevents the production of a void within the via hole during the formation of the via contact since the inner portion of the via hole is filled with the second metal film before the top portion of the via hole is clogged with the second metal film.
In the first method of fabricating a semiconductor device, the first metal film and the second metal film are preferably composed of the same material.
In the arrangement, the first metal film composing the lower interconnect is connected directly to the second metal film composing the via contact. Accordingly, even if electromigration occurs at continuity, the lower interconnect or the via contact is prevented from serving as a migration barrier which interrupts the movement of metal atoms. This prevents the breakage of the interconnect due to an excessive or insufficient quantity of metal atoms adjacent the junction interface between the lower interconnect and the via contact.
In this case, the first metal film and the second metal film are preferably composed of copper.
This reduces the resistance of each of the lower interconnect composed of the
Aoi Nobou
Nakagawa Hideo
Tamaoka Eiji
Ueda Tetsuya
Dang Phuc T.
Matsuhita Electronics Corporation
Nelms David
Nixon & Peabody LLP
Robinson Eric J.
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