Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-05-31
2001-02-20
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185010, C365S185050
Reexamination Certificate
active
06191980
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits, and, in particular, to non-volatile memory cells.
2. Description of the Related Art
A single-poly EEPROM (electronically erasable programmable read-only memory) cell structure implemented in a standard CMOS process is described by K. Ohsaki, N. Asamoto, and S. Takagaki in “A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes,” IEEE Journal of Solid-State Circuits, Vol. 29, No. 3, March 1994, pp. 311-316 (“the Ohsaki paper”), the teachings of which are incorporated herein by reference.
FIGS. 1A and 1B
show a schematic and a topologic view, respectively, of the single-poly EEPROM cell
100
described in the Ohsaki paper (also referred to as the IBM cell). Single-poly EEPROM cell
100
comprises a PMOS transistor MC
1
102
and an adjacent NMOS transistor M
2
104
that share an electrically isolated common polysilicon gate
106
. The common gate
106
works as a floating gate with the inversion layer of the PMOS transistor and p+ diffusions working as a control gate
108
.
The Ohsaki paper describes single poly EEPROM cells in the context of a 0.8-micron standard logic CMOS process. The Ohsaki paper describes two different techniques for erasing the single poly EEPROM cell: one relies on FN (Fowler Nordheim) tunneling between the floating gate
106
and the p+diffusion in the PMOS transistor
102
and the other relies on FN tunneling between the floating gate
106
and the n+ diffusion in the NMOS transistor
104
. In either case, a voltage of sufficient magnitude must be applied across the oxide separating the polysilicon gate from the underlying structure in order to achieve the desired FN tunneling.
Conventional non-volatile memory cells require at least about 90-100A of oxide to separate the polysilicon gate from the underlying structure to maintain data in the cells for a reasonable time (about 10 years). To erase a cell through FN tunneling, the electric field across this tunnel oxide must be at least about 10MV/cm. Thus, to achieve FN tunneling across a 90-100A tunnel oxide, a voltage of at least about 9-10V would need to be applied across the oxide to perform an erase operation.
According to the Ohsaki paper, the erase voltage is applied to the source/drain of the devices. As such, the 9-10V erase voltage would need to be applied to the device junctions. However, in advanced deep sub-micron technologies, the junction breakdown of devices is rapidly decreasing. For example, in some 0.25-micron technologies, junction breakdown voltages are as low as 7V. Moreover, this junction breakdown voltage level will likely continue to decrease as devices are scaled down even more. As such, the single poly EEPROM cell structure described in the Ohsaki paper cannot be effectively implemented for deep sub-micron technologies of at least 0.25 &mgr;m and smaller, because the voltages required to perform an erase operation would likely result in device-threatening junction breakdowns.
SUMMARY OF THE INVENTION
The present invention is directed to a single poly EEPROM (i.e., flash) cell structure that is suitable for deep sub-micron technologies. In certain embodiments of the present invention, a Fowler-Nordheim (FN) erase gate device is added to the single poly cell structure described in the Ohsaki paper, where the erase gate device shares the same common floating gate as the PMOS and NMOS devices, but where the gate capacitance of the erase gate device is much smaller than the total gate capacitance of the floating gate. Typically, the floating gate-to-erase-N-tub capacitance is designed such that the ratio of the floating gate-to-erase-N-tub capacitance is less than about 0.25 times the total floating gate capacitance. According to these embodiments, the cell is erased by applying an erase voltage (e.g., about 9-10V) to the n tub (and thus the source S and drain D) of the erase gate device to provide the necessary voltage across the tunnel oxide to achieve FN tunneling. Since this voltage is less than a typical tub breakdown voltage (i.e., about 13-15V), the single poly flash cell of the present invention can be erased without risking the occurrence of device-damaging breakdowns. In addition, for particular embodiments of the present invention, changes are made to the control gate design (as compared to the cell structure described in the Ohsaki paper) to effectively lower the cell threshold voltage.
The resulting cell can be fabricated with only one additional masking step above a core CMOS logic process, thick-gate oxide. The benefits include: (1) low VDD read operation by lower erased-state cell threshold, (2) higher endurance, (3) longer data retention, (4) lower gate voltage for programming, and (5) if using negative gate voltage during erase, less negative gate voltage for erasure.
In one embodiment, the present invention is a single-poly memory cell, comprising (a) a control device; (b) a switch device; and (c) an erase device comprising an erase gate. The control, switch, and erase devices share a common, polysilicon floating gate configured to retain charge as a result of programming the memory cell. The memory cell is configured to be erased by causing tunneling between the erase gate and the floating gate without causing any junction breakdown within the memory cell.
REFERENCES:
patent: 5615150 (1997-03-01), Lin et al.
patent: 5978274 (1999-11-01), Wang
patent: 6038171 (2000-03-01), McElheney
patent: 6101131 (2000-08-01), Chang
patent: 6125059 (2000-09-01), Hecht
“A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes,” by Katsuhiko Ohsaki et al., IEEE Journal of Solid-State Circuits, vol. 29, No. 3, Mar. 1994, pp. 311-316.
Kelley Patrick J.
Kohler Ross A.
Leung Chung W.
McPartland Richard J.
Singh Ranbir
Dinh Son T.
Lucent Technologies - Inc.
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