Non-latency affected contention prevention during scan-based...

Details Non-latency affected contention prevention during scan-based... Non-latency affected contention prevention during scan-based...

2000-10-04

2001-11-20

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S016000, C714S727000

Reexamination Certificate

active

06320419

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the testing of electronic circuitry, and more particularly to contention prevention in the testing of electronic circuitry.
BACKGROUND OF THE INVENTION
Many schemes for the testing of circuitry exist in the art. One type of test is the “scan-based” test, which scans values into latches which drives the input signals to a path circuit. Each node in the path circuit may be written by one of a multiple of sources. However, when the same node is being written from multiple sources at the same time during scan-based testing, contention occurs, which causes erroneous data to be output from the path circuit. A contention prevention scheme is thus required to avoid this problem.
Many of the conventional contention prevention schemes require the contention prevention circuit (CPC) to be located in the functional timing path of the path circuit.
FIG. 1
illustrates a timing diagram for a conventional skewed write clock scheme for contention prevention. This scheme, typically used in multi-port memory arrays, uses skewed write clock signals for skewed write wordline generation. For n number of write ports in the multi-port memory array, n number of write clock signals could be generated for the same address. For example,
FIG. 1
illustrates the clock signals, WCLKA
102
, WCLKB
104
, and WCLKC
106
, for three ports A, B, and C (not shown). The ports follow their respective clock signals
102
,
104
,
106
. Assume that the ports are written when their respective clock signals transition from low to high. By providing skewed clock signals, port A is written first, then port B, and then port C, but not at the same time. However, with this scheme, functional timing of the path circuit is adversely affected since the CPC implementing this scheme would be in the path of the path circuit. Also, as n increases, the functional timing becomes more adversely affected.
FIG. 2
illustrates a timing diagram for a conventional overlapped write clock scheme for contention prevention. In this scheme, overlapping write clock signals are used for the multi-port memory arrays. Again, as with the skewed write clock scheme illustrated in
FIG. 1
, n number of write clock signals could be generated for the same address. For example, the clock signals, WCLKA
202
, WCLKB
204
, and WCLKC
206
, are for three ports A, B, and C (not shown). When more than one clock signal is high, there is contention and no port is written. Thus, when WCLKA
202
transitions low, contention remains between ports B and C. When WCLKB
204
transitions low, only WCLKC
206
remains high. Since now there is no contention, port C is written. However, this scheme does not prevent contention during scan-based test. It also adversely affects the functional timing of the path circuit in the same manner as the skewed write clock scheme, described above.
FIG. 3
illustrates a conventional gated wordline driver scheme for contention prevention.
FIG. 3
shows a CPC
300
which implements the scheme. With this scheme, only one wordline driver is active at any one time. For example, WCLKA
302
, WCLKB
304
, and WCLKC
306
are the write wordline drives for ports A, B, and C (not shown), respectively, of the multi-port memory array. The CPC
300
prevents WCLKC
306
from becoming active unless WCLKA
302
and WCLKB
304
are both inactive. Thus two or more wordlines are not allowed to be active at the same time, preventing possible contention on the latch node of the memory cell. In this example, port A has the highest priority to write, followed by port B and then port C. However, as the n number of write ports increases, more “legs” must be added to the CPC
300
as the number of low-priority wordline drivers increases to n−1. Thus, functional timing of the path circuit is adversely affected.
Other conventional contention prevention schemes include the use of test clocks separate from the write clocks. With this scheme, test timing assertions guarantee that two of the test clocks are never active at the same time. However, as the number of write ports increase, the number of separate test clocks increases. Also, this scheme requires extra primary inputs at the chip level. Typically only a certain amount of test-related primary inputs are allowed at the chip level.
Accordingly, there exists a need for a method and system for a contention prevention scheme which provides contention prevention during scan-based test without adversely affecting the functional timing of the path circuitry. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for a contention prevention scheme which provides contention prevention during scan-based test without adversely affecting the functional timing of the path circuit. The contention prevention scheme provides a circuit which includes a path circuit gated by a contention prevention circuit (CPC) and the CPC, where the CPC allows functional operation to occur without adversely affecting the functional operation timing, provided that a time skew between two input signals to the CPC is approximately less than a difference between a time delay associated with a scan-based test logic value and a time delay associated with a functional logic value. With a contention prevention circuit tuned in this manner, a static logical value during functional mode is provided, indicating no contention, which avoids adversely affecting the functional timing of the path circuit.


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IBM Technical Disclosure Bulletin, “Method and Design For Applying Stuck Faults In An LSSD Boundary Scan Environment”, vol. 34, No. 10B, Mar. 1992.

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