Thin film transistor and its fabrication

Details Thin film transistor and its fabrication Thin film transistor and its fabrication

1999-09-27

2001-11-13

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S142000, C438S149000, C438S479000, C438S592000, C438S654000

Reexamination Certificate

active

06316295

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor, and more particularly, to a thin film transistor and its fabrication process for reducing leakage current and the number of masks required.
2. Discussion of the Related Art
Many studies have been made of the application of a polysilicon thin film transistor to the active device and peripheral circuits of an active matrix liquid crystal display. A laser annealing is used in the production of thin film transistors using polysilicon. By using a laser annealing, low temperature processes are available for fabrication, and high field effect mobility can be realized.
When polysilicon thin film transistors are used in a liquid crystal display, there are no problems with switching the driving circuit at high frequency due to the characteristics of polysilicon. However, leakage current may increase due to high drain current in the OFF state in the pixel array. Studies are currently conducted on thin film transistors having lightly doped drain (LDD) structures, or offset structures, to decrease the drain electric field, thereby reducing the leakage current. Producing a thin film transistor with an LDD structure or offset gate structure requires additional masking processes compared to producing a conventional thin film transistor.
FIGS. 1A-1D
are flow diagrams illustrating a process for fabricating thin film transistors having an offset structure according to conventional techniques.
Referring to
FIG. 1A
, an amorphous silicon layer is formed on an insulating layer
10
and crystallized by laser annealing. The crystallized silicon layer is patterned by photolithography (using a first mask) to form an active layer
11
.
Referring to
FIG. 1B
, an insulating layer and a metal layer are sequentially formed on the entire surface of the substrate above the insulating layer
10
, and patterned by photolithography (using a second mask) to form gate electrodes
13
and a gate insulating layer
12
. Reference numeral
11
C indicates the channel region of the active layer overlapping the gate electrode
13
.
Referring to
FIG. 1C
, the entire surface is coated with a photosensitive material, and then a photoresist pattern PR is formed (using a third mask), which covers the gate electrode, but exposes a part of the active layer
11
. The photoresist pattern defies an offset region
11
f.
The entire surface is then doped with an impurity to form ohmic regions in the exposed portions of active layer
11
. The ohmic regions are a source region
11
S and a drain region
11
D. Parts of the active layer are blocked from being doped with impurity by the photoresist pattern PR. Thus, the blocked parts of the active layer, except for the channel region
11
C, are offset regions
11
f.
Referring to
FIG. 1D
, insulating material is deposited on the entire surface to form an insulating interlayer
14
. The insulating interlayer
14
is patterned by photolithography (using a fourth mask) to form contact holes T exposing the source and drain regions
11
S and
11
D of the active layer
11
.
Referring to
FIG. 1E
, a metal layer is formed on the entire surface above the insulating layer
10
. The metal layer is patterned by a photolithography (using a fifth mask) to form source and drain electrodes
15
S and
15
D, which are connected to the source and drain regions
11
S and
11
D which were exposed by the contact hole.
In the fabrication process described above, it is necessary to perform five photolithography processes using five masks. In the fabrication of thin film transistors, reducing the number of masking process is as important as reducing the leakage current at the OFF state. This is because the photolithography is a sequential process, which requires complicated and precise processing, such as masking process, photoresist coating, and exposure and development. Therefore reducing the number of masking process desirably affects the productivity and reliability of fabricated products.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a thin film transistor and its fabrication that substantially obviates one or more of the problems due to the limitations and disadvantages of the related art.
An object of the present invention is to provide a thin film transistor with reduced leakage current at the OFF state.
Another object of the present invention is to provide a thin film transistor which requires a small number of masking steps to fabricate.
Additional features and advantages of the present invention will be set forth in the description which follows, and will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure and process particularly pointed out in the written description as well as in the appended claims.
To achieve these an other advantages, and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a thin film transistor including an active layer; a gate insulating layer above the active layer, wherein the active layer includes a portion covered by the gate insulating layer, a first portion of the active layer not covered by the gate insulating layer and a second portion of the active layer not covered by the gate insulating layer; a gate electrode above the gate insulating layer; an offset layer above the first portion of the active layer and above the second portion of the active layer; a source electrode above the first portion of the offset layer; and a drain electrode above the second portion of the active layer.
In another aspect of the present invention, there is provided a method of fabricating a thin film transistor including the steps of forming an active layer above an insulating layer; forming a gate insulating layer above the active layer so as to cover a part of the active layer, wherein the active layer has a first exposed portion and a second exposed portion; forming a gate electrode above the gate insulating layer; forming an offset layer above the first exposed portion of the active layer and above the second exposed portion of the active layer; forming a source electrode above the offset layer and above the first exposed portion of the active layer; and forming a drain electrode above the offset layer and above the second exposed portion of the active layer.
In a further aspect of the present invention, there is provided a method of fabricating a thin film transistor, including the steps of forming an active layer on an insulating substrate; forming an insulating layer and a first metal layer on the active layer; forming a photoresist pattern for forming a gate electrode on the first metal layer; patterning the first metal layer and the insulating layer by using the photoresist pattern as a mask, thereby forming a gate electrode and a gate insulating layer and exposing a part of the active layer; forming an amorphous silicon layer so as to cover the insulating substrate and the active layer; forming a second metal layer on the amorphous silicon layer; patterning the second metal layer and the amorphous silicon layer by a photolithographic process to form an offset layer, a source electrode and drain electrode; and removing the photoresist pattern to expose the surface on the gate electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4999690 (1991-03-01), Rodder
patent: 5200630 (1993-04-01), Nakamura et al.
patent: 5231296 (1993-07-01), Rodder
patent: 5264383 (1993-11-01), Young
patent: 5658805 (1997-08-01), Young
patent: 5693959 (1997-12-01), Inoue et al.
patent: 5744818 (1998-04-01), Yamazaki et al.
patent: 5811836 (1998-09-01), Ha
patent: 5818070 (1998-10-01), Yamazaki et al.

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