Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2000-12-27
2001-11-06
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S083000, C326S086000
Reexamination Certificate
active
06313659
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to chip to chip communications, and, particularly to matching the input impedance of a receiver circuit in a first chip with the output impedance of a driver circuit in a second chip and with the characteristic impedance of a transmission line coupling the driver circuit to the receiver circuit.
As signal rates increase in integrated circuit (chip) technology, many of the chip to chip communications require matched impedances between the driver circuits and the receiver circuits on chips. This is required in order to achieve maximum data transfer rates between a driver circuit and a receiver circuit and to reduce reflection of data signals in the transmission line which couples the driver circuit to the receiver circuit.
An ideal driver-receiver system would consist of a remote driver circuit, a transmission line, and a receiver circuit. In such an ideal driver-receiver system, the driver circuit is a source pulse generator which has a Thevenin equivalent output impedance, Z
Do
, matching the characteristic impedance, Z
To
, of the transmission line and matching the input impedance, Z
Ro
, of the receiver circuit.
Realistically, a non-ideal driver-receiver system implementing chip to chip communication includes a remote driver circuit, a transmission line, an impedance matching circuit, and a receiver circuit. The impedance matching circuit matches the input impedance of a receiver circuit with the output impedance of the remote driver circuit and with the characteristic impedance of the transmission line.
For example,
FIG. 1
shows a block diagram of a driver-receiver system
100
which includes an impedance matching circuit
130
. Driver-receiver system
100
includes a remote driver circuit
110
coupled to transmission line
120
, which is coupled to impedance matching circuit
130
, which in turn is coupled to receiver circuit
140
. Remote driver circuit
110
receives an original data signal, A, and outputs a driver data signal, A
D
, to transmission line
120
. Transmission line
120
transmits driver data signal A
D
and outputs transmission data signal A
T
to impedance matching circuit
130
. Impedance matching circuit
130
outputs an impedance-matched data signal, A
IM
, to receiver circuit
140
. Receiver circuit
140
outputs a receiver data signal, A
R
.
FIG. 2A
shows a first type of known driver-receiver system
210
which includes a first type of known impedance matching circuit
130
. This first type of known impedance matching circuit
130
includes a first resistor
220
, a second resistor
230
, and an inverter
240
. In one case, first resistor
220
and second resistor
230
are external termination resistors which are discrete resistors added to the printed circuit board (PCB) on which the chip with remote driver circuit
110
and the chip with receiver circuit
140
are mounted. In another case, first resistor
220
and second resistor
230
are fabricated into the package that supports the chip with receiver circuit
140
and make the electrical connections available to the PCB wires. In both cases, the parallel combination of the resistances of first resistor
220
and second resistor
230
is set to generate an input impedance for receiver circuit
140
which matches the output impedance of remote driver circuit
110
and the characteristic impedance of transmission line
120
. However, system
210
which includes impedance matching circuit
130
poses several problems. For example, system
210
requires additional work for mounting first resistor
220
and second resistor
230
either on the PCB or in the package which supports the chip with receiver circuit
140
. In addition, system
210
less reliably maintains the input impedance for receiver circuit
140
constant because of the external connections required between the chip with receiver circuit
140
and either the PCB or the package which supports the chip with receiver circuit
140
.
Other types of known driver receiver systems exist which are similar to the first type of known driver-receiver system
210
. For example, instead of using discrete resistors to generate the input impedance of receiver circuit
140
, bipolar transistors are used to generate the input impedance of receiver circuit
140
. In that case, the bipolar transistors are configured as resistors and take the place of first resistor
220
and second resistor
230
in system
210
. In another example, PMOS transistors configured as resistors are used. Both of these alternative versions pose several problems First, they do not effectively maintain the input impedance of receiver circuit
140
constant over temperature. Also, they do not effectively compensate for process variations in the manufacturing of the chips which the impedance matching circuit
130
is supposed to interact with.
FIG. 2B
shows a second type of known driver-receiver system
250
which includes a second type of known impedance matching circuit
130
. This second type of known impedance matching circuit
130
includes a first transistor
260
, a second transistor
270
, and an inverter
280
. A control signal biases first transistor
260
such that the parallel combination of first transistor
260
and second transistor
270
generates an input impedance for receiver circuit
140
which matches the output impedance of remote driver circuit
110
and the characteristic impedance of transmission line
120
. However, system
250
also is subject to problems with temperature and process variations.
For the foregoing reasons, an impedance matching circuit which maintains the input impedance of the receiver circuit constant over temperature variations and over process variations, without the use of external resistors, would greatly benefit chip to chip communications.
SUMMARY OF THE INVENTION
The present invention provides a CMOS impedance matching circuit with an amplifier and a feedback circuit. The amplifier allows control of the impedance by controlling the V/I characteristic. The amplifier is sized to provide the desired impedance. The feedback circuit clamps the maximum excursions of the input signal, thereby maximizing signal speed. It also provides a high impedance dead band to increase the noise margin.
In one embodiment of the present invention, the amplifier includes an amplifier circuit in parallel with an amplifier buffer. The amplifier buffer provides no gain and simply performs the inverting function when no gain is required for impedance matching.
In one embodiment, the amplifier circuit includes a plurality of switchable amplifiers coupled in parallel with each other. Each of the switchable amplifiers has a different gain, and the one with the right amount of gain for the needed impedance matching is chosen using control inputs. Each of the switchable amplifiers is preferably constructed using pull up and pull down circuits, which ensure that the voltage is within the compliance range of the remote driver circuit.
In the absence of an input, the feedback circuit biases the transmission line to the trigger level of the remote receiver circuit, ensuring a quick response when an input is received.
The invention will be better understood by reference to the following detailed description in connection with the following drawings.
REFERENCES:
patent: 4719369 (1988-01-01), Asano et al.
patent: 5134311 (1992-07-01), Biber et al.
patent: 5498990 (1996-03-01), Leung et al.
patent: 6072331 (2000-06-01), Takizawa
patent: 6211714 (2001-04-01), Jeong
Bosnyak Robert J.
Cruz Jose M.
Drost Robert L.
Le Don Phu
Sun Microsystems Inc.
Tokar Michael
Townsend and Townsend / and Crew LLP
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