Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reissue Patent
1997-10-03
2001-10-30
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S378000, C438S202000, C438S206000
Reissue Patent
active
RE037424
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a mixed technology, “smart power”, integrated device containing power transistors and control logic and analog driving circuitry combined in a monolithic silicon chip.
2. Description of the Prior Art
The commercial success of so-called “smart power” integrated circuits, wherein the analog signal processing circuitry, the control logic circuitry and the output power devices are conveniently monolithically integrated in a single chip, originated and sprung from the overcoming of compatibility problems among the different fabrication processes relative to the different integrated devices, often necessarily operating under different supply voltages. Most often, even though non-exclusively, the power section of such integrated circuits employs VDMOS transistors which typically require a driving gate voltage level comprised between about 10 V-20 V.
This makes difficult interfacing the power transistor (e.g. VDMOS) with the driving circuitry. Commonly, in fact, the maximum operating voltage of CMOS transistors used in logic circuitry is 5 V. Conversely, the driving circuitry for power transistors operate at about 12 V, while in order to ensure a driving level on the gate of a VDMOS power transistor of 10 V and if a reasonable process “spread” is accounted for, the supply voltage of CMOS transistors of the relative driving circuit should be at least 15 V. Moreover better operating conditions of a VDMOS power transistor (i.e. a lower resistance R
on
) may be achieved if the driving voltage level on the gate may be raised to 15-20 V, as it is well known to a skilled technician.
In “smart power” type integrated circuits, this particular problem is commonly obviated by using a “level shifter” circuit, which necessarily makes the driving circuit more complicated.
There is a definite need for the availability of CMOS transistors having an operating voltage of about 20 V in a monolithically integrated semiconductor device of the “smart power” type in order to drive directly the output power transistors with a relatively high voltage without employing special level shifter circuits.
On the other hand, in these integrated circuits there are other CMOS and bipolar transistors which are employed, because of their peculiar characteristics, in control logic circuitry and in signal processing circuitry, respectively. Also the utility and reliability of these other integrated devices could be advantageously enhanced if also these other integrated devices could be made capable of withstanding a higher supply voltage than the voltage normally allowed by the physical structure of these integrated devices produced through a mixed-technology fabrication process.
OBJECTIVE AND SUMMARY OF THE INVENTION
In view of this state of the art, the present invention has the main objective of providing, in a monolithically integrated “smart power” type device, CMOS structures and isolated collector, vertical, PNP transistors capable of withstanding a higher operating voltage than the voltage normally withstood by these devices, when they are formed monolithically together in a single chip.
This objective is reached by the integrated device of the invention, as defined in the annexed claims.
Structurally the device is characterized by the fact that it comprises regions of phosphorus doped, n-type silicon of similar diffusion profile extending from the surface of the n-type epitaxial layer wherein the different devices are formed, respectively, through the drain area of n-channel LDMOS transistors extending between the gate electrode thereof and the adjacent isolating field oxide, the body area of p-channel LDMOS transistors, extending between the gate electrode thereof and the adjacent isolation field oxide, the drain area of n-channel MOS transistors, extending between the gate electrode thereof and the adjacent isolation field oxide, and the emitter area of isolated collector vertical PNP bipolar transistors, and by a depth sufficient to contain, respectively, the n
+
doped drain region of n-channel LDMOS transistors, the p
+
doped source region of p-channel LDMOS transistors, the n
+
doped drain region of n-channel MOS transistors and the p
+
doped emitter region of the PNP transistors.
In the case of an n-channel LDMOS transistor, the presence of this auxiliary n-doped region, obtained by implanting phosphorus through the drain area, increases the breakdown voltage because the field intensity between the drain and the gate is reduced while obtaining a reduction too of the conducting resistance (R
on
) of the transistor, which is extremely advantageous when the LDMOS transistor itself is used as an integrated power switching device, as it is often the case in these mixed technology integrated devices.
In the case of a p-channel LDMOS transistor, the same auxiliary n
−
doped region may conveniently constitute a body region which is so formed without other specific additional process steps.
The CMOS structures formed by pairs of complementary LDMOS transistors, when provided with such an n-doped region by phosphorus implantation, become capable of operating with a supply voltage of about 20 V without requiring special precautions, such as “field plates”, thus remaining advantageously compact.
In the case of an n-channel MOS transistor belonging to another type of CMOS structure, the n-doped region, obtained by phosphorus implantation in the drain area of the transistor, reduces the sensitivity to electrical stresses due to hot electrons, by acting as a “drain extension” region; this permits to the transistor to withstand a supply voltage of about 12 V.
In the case of an isolated collector, vertical PNP bipolar transistor, the additional n-doped region obtained by phosphorus implantation through the emitter area of the transistor, permits to improve the transistor's performance transistors by increasing the charge in the base region of the transistor and to increase the “punch-through” voltage between emitter and collector.
The parallel ability of the different CMOS structures and vertical PNP transistors to withstand a specifically increased operating voltage specifically increased permits to build mixed technology integrated circuits (i.e. “smart power” devices) with far less pronounced interfacing problems among the different types of circuits, with enhanced possibilities of fully exploiting the intrinsic peculiarities of the different devices and with a higher degree of reliability
.
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S. M. Sze,Semiconductor Devices Physics and Technology, John Wiley & Sons, New York (1985) pp. 401-2.
Contiero Claudio
Galbiati Paola
Zullino Lucia
Carlson David V.
Crane Sara
Galanthay Theodore E.
Jorgenson Lisa K.
STMicroelectronics S.r.l.
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