Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-02-08
2001-12-11
Bowers, Charles (Department: 2813)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06330704
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for deriving the parasitic parameters of conductors. More specifically, the invention relates to a method for calculating the capacitance between conductors and resistance in conductors in an integrated circuit.
2. Description of the Related Art
As the feature size of advanced integrated circuits continues to decrease and transistor switching times become ever shorter, on-chip signal delay is increasingly dominated by the RC delay associated with the signal lines. In order for circuits to produce meaningful and reliable results, the circuit models used must include accurate values for the capacitances and resistances of the signal lines. The complex dielectric structures present in advanced chip and package technologies can have a substantial effect on the signal line capacitance values. The only practical method for obtaining accurate capacitance values for such geometries is detailed numerical solution.
In the electrical modeling of packages it has long been recognized that the capacitance of signal lines plays an important role in determining signal propagation delays. For this reason, it has been standard practice to carry out detailed numerical calculations of the circuit parameters (e.g. R, L, C) of signal lines. These computed circuit parameters for signal lines and circuit models for the drivers and receivers are then used to predict such properties as signal delay and crosstalk for boards and modules.
Until recently, the situation was quite different for the analysis of signal delay in integrated circuits on a single chip. In the past, signal delay was dominated by the switching time associated with the individual transistors in the circuit, and only for a select few signal lines was an accurate circuit model needed. One would typically use a crude estimate of the capacitance per unit length of a critical signal line, and omit all coupling-capacitances and the self-capacitances of other wires. The capacitances per unit length of the few important signal lines were often obtained from simple area-perimeter formulas.
With recent advances in chip technology, the switching time of transistors has become exceedingly small. As a result, the performance of on-chip circuits has become increasingly limited by the RC delay associated with signal lines. Each new decrease in feature size increases the portion of signal delay due to the signal lines. It is thus becoming more critical that accurate capacitances for signal lines be included in equivalent circuit models of on-chip circuits.
Others have attempted to determine capacitances and resistances related to circuit signal lines. For example, the following references are known:
1.
5,295,088 . . . March 1994
Hartog, et al.
2.
5,452,224 . . . Sept 1995
Smith, et al.
3.
5,610,833 . . . March 1997
Chang, et al.
4.
5,706,206 . . . Jan 1998
Hammer, et al.
5.
5,734,583 . . . March 1998
Shou, et al.
6.
5,751,591 . . . May 1998
Asada, et al.
7.
5,761,080 . . . June 1998
DeCamp, et al.
8.
5,838,582 . . . Nov 1998
Mehrotra, et al.
9. Chang, “Analytical IC Metal-Line Capacitance Formulas”, IEEE Transactions on Microwave Theory and Techniques, (September 1976), pp. 608-611.
10. Ruehli, et al., “Efficient Capacitance Calculations for Three-Dimensional Multiconductor Systems”, IEEE Transactions on Microwave Theory and Techniques, Vol. 21, No. 2, (February 1973), pp. 76-82.
11. Sakurai, T. and K. Tamaru, “Simple Formulas for Two and Three Dimensional Capacitances”, IEEE Trans. Electron Devices, Vol. ED-30, No. 2, pp. 183-185, 1983.
12. McCormick, “EXCL: A Circuit Extractor for IC Designs”, IEEE (1984), pp. 616-623.
13. van der Meijs, N. P. and A. J. van Genderen, “An Efficient Finite Element Method for Submicron IC Capacitance Extraction”, 26th ACM/IEEE Design Automation Conference, Paper 40.2, (1989), pp. 678-681.
14. Janak, James F. and David D. Ling et al., “C3DSTAR: A 3D Wiring Capacitance Calculator”, ICCAD-89 Digest, (November 1989), pp. 530-533.
15. Nabors, et al., “Fast Capacitance Extraction of General Three-Dimensional Structures”, IEEE Transactions on Microwave Theory and Techniques, Vol. 40, No. 7, (1992), pp. 1496-1506.
Several different methods have been used to obtain capacitances and resistances for signal lines. These include exact closed-form solution, approximate formulas (such as area-perimeter formulas), and detailed numerical solution. Closed-form exact solutions can be obtained for highly-symmetric 2D and 3D geometries through the use of separation of variables. Some 2D problems can be solved by conformal mapping (e.g. [9]). These exact analytic methods are elegant and produce closed-form expressions for the capacitances. However, they are severely limited in the variety of geometries that can be analyzed, and are incapable of handling the geometries typical of advanced chips and packages.
Simple approximate formulas are often used in circuit extraction programs.
Some approximate formulas, such as area-perimeter formulas, arc based on drawing a rough analogy between the actual geometric configuration and some idealized geometry for which one can find an exact solution. Such uncontrolled approximations can be verified only by hardware measurement and/or detailed numerical computation. Other simple formulas are obtained by fitting curves to capacitance values computed numerically (e.g. [1], [2], [3], [4], [5], [7], [8], [11], [12]). Approximate formulas based on anything other than detailed numerical solution or hardware measurement are incapable of producing sufficiently accurate capacitance values for advanced chips and packages.
FIG. 1
depicts a prior art 2D representation of the self-capacitance and cross-capacitance between different conductor nets
10
,
20
,
30
. A conductor net can be thought of as a set of electrically connected conductors. As used herein, conductor net and interconnect are substantially synonamous. A driven conductor net with specified non-zero potential is referred to as the active net. Conductor nets which are near to the active net with specified zero potential are referred to as victim nets. The self-capacitance of the active net and the cross-capacitance between the active net and victim nets are used to calculate the delay of the active net and the coupling between the active and victim nets. The self-capacitance and cross-capacitances are decomposed into contributions due to overlap
15
,
35
, lateral
25
, and fringe
40
capacitance effects. All capacitance effects (including overlap, lateral and fringe) have components due to wire to substrate and wire to wire capacitance. Though overlap, lateral and fringe capacitances are often treated separately, such distinctions are artificial; capacitance is really a single, three-dimensional electromagnetic problem. How closely a particular parasitic extraction algorithm models this three-dimensional physical reality is often characterized as “two-dimensional” (2D) or “three-dimensional” (3D). The calculation of any capacitive value is always three-dimensional (requiring width, length and thickness of the conductors as well as distance between them), but the terms “2D”, “2.5D” and “3D” refer to how an algorithm attacks the problem.
The 2D and 2.5D algorithms typically superimpose the numerical field solutions of simple patterns to obtain a capacitance and resistance estimate for an actual conductor net. However because the conductor net geometry is dissimilar to the patterns, the pattern fields cannot be superimposed, which introduces a nonlinear geometrical error. As a result, 2D and 2.5D algorithms that use simple patterns are inherently inaccurate. Further, irregular conductor net geometries are not identified as precharacterized patterns. The capacitance contribution due to these unidentified geometries can be discarded, interpolated between nearby patterns, or a numerical solver is used to compute a solution. All of these faults show that 2D and 2.5D a
Bachtold Martin
Ljung Per
Bowers Charles
Coyote Systems, Inc.
Pert Evan
Townsend and Townsend / and Crew LLP
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