Static information storage and retrieval – Read/write circuit – Sipo/piso
Reexamination Certificate
2000-08-21
2001-12-18
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Sipo/piso
C365S185200, C365S185240
Reexamination Certificate
active
06331960
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a nonvolatile semiconductor storage device and a method for using it, and more particularly to a multi-level memory, and its usage, which can store multi-level (multi-value) data in memory cells made of stacked MOS transistors.
A flash memory for storing multi-level data is disclosed in detail in ISSCC '95 Digest of Technical Papers, p. 133, for example. The memory has an architecture using flash cells as its reference cells to control the current flow into the reference cells and to cope with the read-out potential in accordance with the distribution of threshold values of the cells.
A process for reading data from a NAND flash memory includes random access for reading data of one row of memory cell arrays and for storing it in registers, and subsequent reading of the storage of the registers. When a four-value memory is to be read three times, reading and conversion into a two-value data need the time
3t
R
+3t
S
+t
conv
where t
R
is the random access time, t
S
is the time for reading registers, and t
conv
is the time for conversion into a two-value data. In a particular case where the random access time t
R
is 10 &mgr;S, the register reading time t
S
is 25.6 &mgr;S for reading 512 bytes in 50 nS, and the time t
conv
for conversion into a two-value data is 5 &mgr;S, the total time for reading thrice and for conversion into two values amounts in
10×3+25.6×3+5=111.8 &mgr;S
The above multi-level memory involves the following problems
(1) A 2″-value memory needs n sense amplifiers. Specifically, a four-value memory needs two sense amplifiers, and an eight-value memory needs three sense amplifiers. Thus the multi-level memory requires a Larger area for sense amplifiers.
(2) The number of reference cells is fixed at the time of its design and cannot be flexibly changed later. In a particular case where the number of reference cells is four, the memory must be a four-value memory even if the cells are uniform enough to realize a more-value memory. In another case where a four-value memory cannot be realized due to varieties in process parameters during fabrication, although it will be used as a two-value memory, all the sense amplifiers and other circuit elements intended for use with the four-value memory become invalid, and result in an substantial increase in cost as compared with an originally two-value memory.
(3) The area occupied by sense amplifiers is too large to exactly cope with the distribution of cells within the chip.
(4) Reading from a NAND flash memory takes time against the demand for high-sped reading.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a nonvolatile semiconductor storage device for multi-level storage, and a method of using it, which is flexibly responsive to the number of multiple levels and enables minimization of the chip size.
A further object of the invention is to provide a nonvolatile semiconductor storage device, and a method for using it, which can be read at a high speed.
According to the first aspect of the present invention there is provided a nonvolatile semiconductor memory device comprising:
nonvolatile memory cells each including a source and a drain both formed on one surface of a semiconductor substrate, and including a floating gate and a control gate which are stacked on the semiconductor substrate above a portion between the source and the drain via insulation films;
a word line driving circuit for applying one of a plurality of predetermined potentials to said control gates of the nonvolatile memory cells, depending on a control data introduced into said memory device; and
writing and sensing circuit for applying a potential to said drains in accordance with write data introduced into said memory device and for detecting and amplifying the current flowing between the drain and the source in each said nonvolatile memory cell.
According to the second aspect of the present invention, there is provided a method for using a nonvolatile semiconductor memory device including nonvolatile memory cells which each have a source and a drain both formed on one surface of a semiconductor substrate, and including a floating gate and a control gate which are stacked on the semiconductor substrate above a portion between the source and the drain via insulation films, comprising:
when a first level of multi-level data including at least a first level and a second level is to be written, repeating a series of behaviors until writing of said first level is completed, said series of behaviors including: applying a predetermined write voltage between said control gate and said drain to introduce a charge into said floating gate and to change the threshold level of said nonvolatile memory cell; applying a voltage responsive to said first level to said control gate and detecting and amplifying a current flowing between the source and the drain of said nonvolatile memory cell to perform verify reading; and confirming whether the writing of said first level is finished or not;
when a second level of said multi-level data is to be written, repeating a series of behaviors until writing of said second level is completed said series of behaviors including: applying said write voltage between said control gate and said drain to introduce a charge into said floating gate and to change the threshold level of said nonvolatile memory cell; applying a voltage responsive to said second level to said control gate and detecting and amplifying a current flowing between the source and the drain of said nonvolatile memory cell to perform verify reading; and confirming whether the writing of said first level is finished or not.
According to the third aspect of the present invention, there is provided a method for using a nonvolatile semiconductor memory device including nonvolatile memory cells which each have a source and a drain both formed on one surface of a semiconductor substrate, and including a floating gate and a control gate which are stacked on the semiconductor substrate above a portion between the source and the drain via insulation films, comprising:
when a first level of multi-level data is to be written, repeating a series of behaviors until writing of said first level is completed, said series of behaviors including: applying a predetermined write voltage between said control gate and said drain to introduce a charge into said floating gate and to change the threshold level of said nonvolatile memory cell; applying a voltage responsive to said first level to said control gate and detecting and amplifying a current flowing between the source and the drain of said nonvolatile memory cell to perform verify reading; and confirming whether the writing of said first level is finished or not;
when a second level of said multi-level data is to be written, repeating a series of behaviors including a first step and a second step until writing of said second value is completed, said first step including: applying said write voltage between said control gate and said drain to introduce a charge into said floating gate and to change the threshold value of said nonvolatile memory cell by a large amount than that for writing said first value; applying a voltage responsive to said second value to said control gate and detecting and amplifying a current flowing between the source and the drain of said nonvolatile memory cell to perform verify reading; and confirming whether the writing of said first value is finished or not, and said second step including: applying said write voltage between said control gate and said drain to introduce a charge into said floating gate and to change the threshold value of said nonvolatile memory cell; applying a voltage responsive to said second value to said control gate and detecting and amplifying a current flowing between the source and the drain of said nonvolatile memory cell to perform verify reading; and confirming whether the writing of said first value is finished or not.
According to th
Banner & Witcoff , Ltd.
Fears Terrell W.
Kabushiki Kaisha Toshiba
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