Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1997-11-28
2001-02-06
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S648000, C438S584000
Reexamination Certificate
active
06184120
ABSTRACT:
BACKGROUND OF THE INVENTION
Description of the Related Art
The present invention relates to a method of forming a semiconductor device, and more particularly to a method of forming a metal plug buried in an insulation layer over a semiconductor substrate and an interconnection extending over the insulation layer so as to be connected to the metal plug.
One of the conventional methods for forming the buried metal plug and the interconnection is disclosed in Japanese laid-open patent publication No. 5-275366. A conductive plug is buried in the insulation film before a top portion of the conductive plug and a top surface of the insulation film are planerized for subsequent formation of an interconnection layer extending over the planarized surface of the insulation film.
The above method will be described in detail with reference to
FIGS. 1A through 1D
. With reference to
FIG. 1A
, an insulation film
2
A is formed on a top surface of a semiconductor substrate
1
. A contact hole
3
is formed in the insulation film
2
A. A tungsten film
7
is deposited by a chemical vapor deposition over the insulation film
2
A and within the contact hole
3
so that the tungsten film
7
within the contact hole
3
is in contact with the semiconductor substrate
1
. With reference to
FIG. 1B
, a first chemical mechanical polishing method is made wherein a polishing rate of the tungsten film
7
is much higher than a polishing rate of the insulation film
2
A so that the tungsten film
7
over the insulation film
2
A is removed and a surface region of the insulation film
2
A is also removed as well as the tungsten film
7
within the top portion of the contact hole
3
is further removed. As a result, an overpolishing of the tungsten film
7
within the top portion of the contact hole
3
appears to form a recess
8
at the top portion of the contact hole
3
. The top portion of the remaining tungsten plug
7
A within the contact hole
3
is leveled slightly lower than the top surface of the insulation film
2
A.
With reference to
FIG. 1C
, a second chemical and mechanical polishing is made wherein a polishing rate of the tungsten film
7
is much lower than a polishing rate of the insulation film
2
A so that mainly the surface region of the insulation film
2
A is polished whereby the top surface of the insulation film
2
A is leveled to the top portion of the tungsten plug
7
A.
With reference to
FIG. 1D
, an interconnection layer
9
is entirely deposited on a leveled or planarized surface of the insulation film
2
A with the tungsten plug
7
A. The interconnection layer
9
is then patterned to form an interconnection which is in contact with the top portion of the tungsten plug.
The above conventional method has the following three problems.
First, in order to level the top portion of the tungsten plug to the insulation film
2
A, two chemical and mechanical polishing processes are required as described above. This makes the fabrication process complicated.
Second, the tungsten plug and the interconnection layer are formed by two deposition processes and two chemical and mechanical polishing processes in separate processes as described above. This makes the fabrication process complicated.
Third, the increase in resistance of the connection portion between the tungsten plug and the interconnection or any disconnection between the tungsten plug and the interconnection may be caused because the tungsten plug and the interconnection layer are deposited in separate processes as described above.
In the above circumstances, it had been required to develop a novel method of forming a buried plug and an interconnection over the same free from the above three problems.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel method of forming a buried plug and an interconnection over the same free from the above three problems.
It is a further object of the present invention to provide a novel method of forming a buried plug and an interconnection over the same free from any increase in resistance of a connection portion between the tungsten plug and the interconnection.
It is a still further object of the present invention to provide a novel method of forming a buried plug and an interconnection over the same free from any disconnection between the tungsten plug and the interconnection.
It is yet a further object of the present invention to provide a novel method of forming a buried plug and an interconnection over the same which allows reduced umber of the fabrication processes.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.
The present invention provides a method of forming a buried plug and an interconnection over the same. A conductive film is deposited not only over a top surface of an insulation film extending over a semiconductor substrate but also within a contact hole formed in the insulation film so that the conductive film over the top surface of the insulation film has a thickness which is thicker than a predetermined thickness. A top surface of the conductive film is planarized so that the conductive film over the insulation film has the predetermined thickness whereby an interconnection layer is unitary formed with a conductive plug conductive film buried within the contact hole.
REFERENCES:
patent: 4960732 (1990-10-01), Dixit et al.
patent: 5166093 (1992-11-01), Grief
patent: 5244534 (1993-09-01), Yu et al.
patent: 5356836 (1994-10-01), Chen et al.
patent: 5527423 (1996-06-01), Neville et al.
patent: 5554565 (1996-09-01), Liaw et al.
patent: 5686355 (1997-11-01), Sumi et al.
patent: 5700716 (1997-12-01), Sharan et al.
patent: 5714038 (1998-02-01), Kim
patent: 5759905 (1998-06-01), Pan et al.
patent: 5801098 (1998-09-01), Fiordalice et al.
patent: 5837608 (1998-11-01), Choi
patent: 5847463 (1998-12-01), Trivedi et al.
patent: 5893749 (1999-04-01), Matumoto et al.
patent: 5911113 (1999-06-01), Yao et al.
patent: 2-98935 (1990-04-01), None
patent: 5-275366 (1993-10-01), None
patent: 6-349826 (1994-12-01), None
patent: 5-17918 (1996-01-01), None
patent: 8-288391 (1996-11-01), None
patent: 17453 (1998-06-01), None
Wolf, S; Silicon Processing for the VLSI Era vol. 2: Process Integration, 1990 pp. 189-194).olf (Silicon Processing for the VLSI Era vol. 2: Process Integration, 1990 pp. 189-194).
Wolf, S.; Silicon Processing for the VLSI Era vol. 2: Process Integration, Sunset Beach, CA, p.p., Jan. 1990.
Lattin Christopher
NEC Corporation
Tsai Jey
Young & Thompson
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