Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
1999-11-05
2001-02-06
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000
Reexamination Certificate
active
06185138
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a method and device for testing random access memory, and particularly to a method and device for testing dynamic random access memory (DRAM) devices.
2. Background of the Invention
There are two known types of semiconductor memory, one referred as volatile memory and the other referred to as non-volatile memory. In volatile memories the stored data is lost when the power supply is removed from the semiconductor device. A non-volatile memory, on the other hand, retains the data stored for extended periods after the power supply to the device has been removed. In a computer or related systems, non-volatile memory is used for long-term storage of programs and data which seldom or never changes, and volatile memory devices are used for the short-term storage of program instructions and data during the execution of a program.
Volatile memory devices may be divided into two categories. Static Random Access Memory (SRAM) consists of flip-flop latches such that each SRAM latch maintains a bit of data so long as power is provided to the SRAM. In dynamic memories, including DRAM devices, a charge representing a data bit is stored on a capacitor. A bit of data is maintained in a DRAM cell in part by periodically refreshing the cell with data previously stored therein, as explained below.
Conventional DRAM cells employ a single transistor architecture wherein the memory cell comprises a storage capacitor having a first terminal connected to a reference voltage, such as Vss, and a second terminal connected to a pass and/or transmission gate transistor. The pass gate transistor serves to transport charge to the storage capacitor, and also to read the charged or uncharged state of the storage capacitor. The gate electrode of the pass/transmission gate transistor is tied to a word line decode signal and the drain electrode thereof is connected to a bit line. Data is stored in the memory cell as a charge on the storage capacitor. However, because data is stored in a dynamic memory cell as a charge on a capacitor and because memory cells experience leakage current either from the storage capacitor or the pass gate transistor, the stored charge in a dynamic memory cell, particularly a stored charge representing a high logic level, decays over time. Each bit of data stored in a DRAM device must therefore be periodically refreshed before it has irretrievably decayed.
The core of a DRAM is typically partitioned into arrays or blocks of memory cells, with each array including a plurality of rows of memory cells and with the cells in each row being connected to a respective one of a plurality of word lines. Memory cells in each column of cells in an array are connected to a respective one of a plurality of bit lines. Bit lines are grouped in pairs such that when data from a memory cell is read onto a first bit line of a bit line pair, the second bit line of the bit line pair is provided with a voltage level that is representative of a signal between a low logic level and a high logic level, relative to the amount of charge that can be placed thereon by a charge stored in a memory cell. This difference in voltage levels between the bit lines of the bit line pair is the differential to which an associated sense amplifier operatively responds.
Sense amplifiers are typically connected to the bit lines of dynamic memory to sense the small change in potential appearing on the bit lines following a memory cell read operation and to drive the bit lines to the appropriate full reference voltage level, such as Vdd or Vss. Once the sense amplifier drives the bit line to the full reference voltage level, the memory cell from which data was read is refreshed with the full reference voltage signal appearing on the bit line.
It is customary to test both the functionality and timing of integrated circuits in order to ensure that the final product performs as specified. With respect to dynamic memory, it is customary to write test patterns into the memory array to test the ability of dynamic memory cells to maintain a stored charge. Such testing screens dynamic memory devices having storage capacitors which sufficiently maintain a stored charge from those dynamic memory devices having “weak” cells which fail to sufficiently maintain a stored charge. For example, storing a charge in a memory cell representing a high logic level and later retrieving the stored charge will test the extent of leakage current associated with the particular memory cell and distinguish dynamic memory devices which perform as specified from those dynamic memory devices possessing an excessive level of leakage current. In order to test the ability of a dynamic memory cell having stored therein a logic high level to maintain its charge, it is commonplace to write a logic high value into a memory cell while writing a logic low value into its surrounding cells.
On-chip test circuitry such as Built In Self Test (BIST) circuitry provides for an increase in the controllability and observability of nodes (segments interconnecting distinct electrical components) within an on-chip memory device so as to increase the ability to access and hence test the memory device. The use of BIST techniques is particularly necessary for testing memory devices which are embedded within an integrated circuit chip. In situations where more than one embedded memory device is located on an integrated circuit chip, additional on-chip test circuitry has been previously employed in association with the embedded memory devices so that the BIST circuitry would not have to be tailored to the individual embedded memory devices. For instance, a pair of read only memory (ROM) cells storing a low logic level and a high logic level have been selectively connected to the bit line pairs of dynamic memory devices so as to increase the controllability of the bit lines, thereby simplifying the writing of test data patterns into the memory arrays and expanding the ability to apply various test patterns to the memory devices. The ROM cell pair has comprised a first transistor hardwired to the low reference voltage level and a second transistor hardwired to the high reference voltage level.
The aforementioned connection of ROM cells to each bit line of a memory device, however, occupies an appreciable amount of space on the integrated circuit. Accordingly, there exists a need to efficiently access memory devices embedded within an integrated circuit chip for purposes of better testing the embedded memory device, taking into consideration size constraints, node accessibility, chip-level pin limitations, and test vector programmability for the embedded memory device.
SUMMARY OF THE INVENTION
Embodiments of the present invention overcome the shortcomings of prior methods and apparatuses for testing memory devices and satisfies a significant need for an effective technique for testing random access memory (RAM). The present testing method is applicable for stand-alone, off-the-shelf memory chips but is especially suited for one or more memory devices embedded within an integrated circuit, such as a microprocessor chip or an application specific integrated circuit (ASIC). A dynamic memory device and corresponding test circuitry embedded within an ASIC may, for example, advantageously utilize additional metal interconnect layers to perform test-related functions not commonly available in stand-alone, off-the-shelf dynamic memories while occupying relatively little additional silicon space on the integrated circuit chip.
According to embodiments of the present invention, there is provided an array of one or more rows of field-effect transistors, with each transistor being operatively associated with a selected bit line pair of the dynamic memory. A single control line is connected to the gate electrode of each transistor in a row of transistors, and different control lines are connected to the gate electrodes of transistors in different rows of transistors. The source electrode of each transistor i
Elms Richard
Galanthay Theodore E.
Jorgenson Lisa K.
Phung Anh
STMicroelectronics Inc.
LandOfFree
Method and apparatus for testing random access memory devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for testing random access memory devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for testing random access memory devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2577617