Semiconductor device with insulated gate transistor

Details Semiconductor device with insulated gate transistor Semiconductor device with insulated gate transistor

1995-04-14

2001-11-13

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S618000

Reexamination Certificate

active

06316813

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device which is used as various semiconductor integrated circuits and, more particularly, to an insulated transistor which is suitable for use as an ULSI.
2. Related Background Art
As a transistor for use in an ULSI, a transistor having a gate length of a submicron size is being developed due to the advancement of the fining processing technique.
FIG. 10
is a schematic cross sectional view showing a LDD (lightly doped drain) structure as a typical MOS type field effect transistor (hereinafter, referred to as an MOSFET). Reference numeral
201
denotes a P type semiconductor substrate;
202
a field oxide film;
203
and
204
n
+
layers of source and drain regions, respectively;
205
a gate insulative film;
206
a gate electrode;
207
and
208
n
−
layers provided to reduce the field concentration near gates of source and drain, respectively;
209
a channel doped layer provided by ion implantation in order to set a threshold value to a desired value; and
210
a p
+
layer.
However, the transistor with the above structure has the following problems.
First, a drain current I
D
and a mutual conductance (gm) are small due to the n
−
layers
207
and
208
. Second, mobility of the carrier decreases. Third, a gate width W cannot be fined by the scaling similar to that of a gate length L.
The above problems will now be described in detail hereinbelow.
FIG. 11
is a graph showing an example of the relation between the channel length and the drain current which has been disclosed in K. Yano, M. Aoki, and T. Masuhara, “Extended Abstracts of the 18th (1986 International) Conference on Solid State Devices and Materials”, pages 85-88, 1986. In the above literature, the cases of drain voltages of 0.1V and 5V and temperatures of 77° K and 300° K are compared. It will be understood from
FIG. 11
that a decrease in channel length and an increase in drain current are not proportional as shown by broken lines XA but are as shown by solid lines XB because of a parasitic drain resistance by the n
−
layers
207
and
208
. XC denotes actual measured values. Since a large drain current is not derived as mentioned above, the mutual conductance characteristics (gm characteristics) deteriorate.
A scaling rule of a typical MOSFET is shown in the following Table 1.
TABLE 1
Parameter
Scaling ratio
Channel length
1/K
Channel width
1/K
Gate oxide film thickness
1/K
Junction depth
1/K
Depletion layer thickness
1/K
Channel impurity concentration
  K
Voltage
1/K
As will be understood from Table 1, to prevent a punch through current between the source and the drain in association with the realization of the fine channel length L, it is sufficient to raise an impurity concentration N
a
of a region serving as a channel. However, when the impurity concentration of the channel becomes high, the mobility of the carrier decreases due to impurity scattering and the gm characteristics deteriorate. Therefore, separate from the above method, in order to prevent the punch through current, there is also considered a method whereby the p
+
layer
210
is formed at a position near the layer of the gate insulative film
205
. However, even in the case using such a method, a field strength in the vertical direction increases for the carrier moving direction and the carrier mobility decreases in accordance with a correlation as shown in FIG.
12
. [
FIG. 12
shows the relation between the field strength (axis of abscissa) in the vertical direction and the mobility (axis of ordinate) disclosed in A. G. Sabnis et al., “IEDM” pages 18-21, 1979. XD, XE, and XF denote actual measured values when the power source voltage is set to 0.0V, −5.0V, and −20.0V, respectively.]
That is, the MOSFET whose gate length L lies within a range from 0.5 to 0.8 &mgr;m can improve the characteristics to a certain degree by the scaling rule of Table 1. However, if the gate length L is smaller, remarkable deterioration of the drain current I
D
, gm characteristics, and the like starts. In addition, when the gate length is further made fine, a ratio of the wiring portions in the whole region further increases, so that a transistor having higher gm characteristics is demanded. However, to satisfy such a requirement, there is only a method of increasing the gate width W in the present situation. Such a method cannot accomplish the inherent object to fine.
The above-described problems similarly occur even in a GOLD (Gate Overlap Lightly doped Drain) type MOSFET which is called an improved type of the LDD type MOSFET.
Therefore, to improve the problems of the MOSFET having the foregoing construction, there is an SGT (Surrounding Gate Transistor) having a structure in which four gate electrodes are arranged so as to face one another as proposed in H. Takato, K. Sunoushi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, and F. Masuoka, “IEDM (International Electron Device Meeting)”, pages 222-225, 1988. The structure of the SGT is shown in FIG.
13
.
In
FIG. 13
, reference numeral
215
denotes a substrate;
216
a p well layer;
217
a source region;
218
a gate electrode;
219
a gain insulative film;
220
a drain region; and
221
a leading electrode of a drain. In the above structures, since the gate electrode
218
is formed so as to surround the channel region, there are advantages such that the field concentration is reduced, an adverse influence by a hot carrier or the like is reduced, and the potential of the channel portion can be easily controlled by the gate, and the like.
In addition to the above structure, there has also been proposed an SOI type MOSFET structure such that an Si mesa structure is formed on an SiO
2
layer on an Si substrate and a gate oxide film is formed on the mesa side wall (refer to Masahiro Siraki, Junichi Iizuka, Takashi Iwai, Seiichiro Kawamura, Nobuo Shirasaki, and Motoo Nakano, “The 49th Lecture Meeting of the Society of Applied Physics, A Collection of Lectures”, Vol. 2, Autumn, 6a-B-7, page 656, 1988.)
As results of that an examination was carefully performed and many experiments were repetitively executed with respect to each of the conventional examples which have been described in detail above, it has been found that the OFF characteristics of the transistor are deficient and the operation is unstable in spite of the above structure.
It is believed the above-noted problems occur because all of the Si regions in which the channels are formed are covered by an SiO
2
insulative film except the interface between the source and drain regions. That is, the Si region is in a complete floating state and its potential cannot be fixed and the operation becomes unstable. Further, for a period of time of the ON state of the transistor, at a moment when the transistor is turned off, the minority carriers (for instance, electrons in the case of the p type MOSFET) generated in the Si region cannot escape to any location but remain until they are recombined and extinguished in the Si region, so that the OFF characteristics deteriorate.
SUMMARY OF THE INVENTION
In order to solve the above technical problems, it is an object of the invention to provide a semiconductor device in which low electric power consumption and high operating speed are accomplished by a construction which is suitable to fine work.
To accomplish the above object, according to the invention, there is provided a semiconductor device comprising source regions, drain regions, channel regions provided between the source and drain regions and gate electrodes provided for the channel regions through gate insulative films. A semiconductor region having the same conductivity type as that of the channel region and an impurity concentration higher than that of the channel region is provided so as to be in contact with the channel region. The gate electrode has at least two opposite portions which face each other and is arranged so that the opposite portions have surfaces which intersect

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