Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-11-22
1998-10-20
Donaghue, Larry D.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395387, 395580, 395581, 395584, 395585, 395586, 39580023, 39580041, 39580042, 711 2, 711 6, 711202, 711203, 711204, 711206, 711212, G06F 932, G06F 942
Patent
active
058260749
ABSTRACT:
A processor has 64-bit operand execution pipelines, but a 32-bit branch pipeline. The branch pipeline contains registers to hold the lower 32-bit sub-addresses of 64-bit target and sequential addresses for conditional branches which have been predicted but not yet resolved. A shared register contains the upper 32 address bits for the target and sequential sub-addresses. All 32-bit target and sequential sub-address registers in the branch pipeline share the single 32-bit shared register holding the upper 32 address bits. The branch pipeline can only process instructions with the same upper 32 address bits, which define a 4 Giga-Byte super-page. When an instruction references an address in a different 4 Giga-Byte super-page, then the branch pipeline stalls until all other branch instructions have completed. The new super-page's upper 32 address bits are then loaded into the shared register. A super-page crossing is detected by a carry out of bit 32 in the 32-bit target or sequential address adders. Branches crossing to a new super-page are always predicted as taken. The super-page address is incremented during mis-prediction recovery when the sequential instruction stream crosses to a new super-page.
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Donaghue Larry D.
Follansbee John
S3 Incorporated
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