Method of forming bumps for flip chip applications

Details Method of forming bumps for flip chip applications Method of forming bumps for flip chip applications

1999-08-09

2001-10-09

Kunemund, Robert (Department: 1763)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S720000, C438S959000

Reexamination Certificate

active

06300250

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming solder bumps for flip-chip applications.
(2) Description of the Prior Art
A continued decrease in semiconductor device feature size, a decrease that is driven by the dual requirements of improved device performance and reduced device manufacturing cost, has over the years resulted in placing increased emphasis on device packaging. This trend has further, due to a significant increase in semiconductor device density, placed increased emphasis on device or package I/O capabilities. The metal connections, which connect the Integrated Circuit to other circuit or system components, have therefore become of relative more importance and potentially have, with the further miniaturization of the IC, an increasingly negative impact on the circuit performance. If the parasitic capacitance and resistance of the metal interconnections increases, the chip performance can be degraded significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires.
One of the approaches that has been taken to solve these packaging problems is to develop low resistance metal (such as copper) for the wires while low dielectric materials are used in between signal lines. Another approach to solve problems of I/O capability has been to design chips and chip packaging methods that offer dependable methods of increased interconnecting of chips at a reasonable manufacturing cost. This has led to the development of Flip Chip Packages.
Flip-chip technology fabricates bumps (typically Pb/Sn solders) on Al pads on the chips and interconnects the bumps directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package medium through the shortest paths. These technologies can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger and to more sophisticated substrates that accommodate several chips to form larger functional units.
The flip-chip technique, using an area I/O array, has the advantage of achieving the highest density of interconnection to the device combined with a very low inductance interconnection to the package. However, pre-testability, post-bonding visual inspection, and Coefficient of Thermal Expansion (CTE) matching to avoid solder bump fatigue are still challenges. In mounting several packages together, such as surface mounting a ceramic package to a plastic board, the TCE mismatch can cause a large thermal stress on the solder-lead joints that can lead to joint breakage caused by solder fatigue from temperature cycling operations.
The packaging substrate is generally used for Ball Grid Array (BGA) packages but can also be used for Land Grid Array (LGA) and Pin Grid Array (PGA) packages.
Prior Art substrate packaging uses ceramic and plastic flip chip packaging. Ceramic substrate packaging is expensive and has proven to limit the performance of the overall package. Recent years has seen the emergence of plastic substrate flip chip packaging, this type of packaging has become the main stream design and is frequently used in high volume flip chip package fabrication. The plastic substrate flip chip package performs satisfactorily when used for low-density flip chip Integrated Circuits (IC's). If the number of pins emanating from the IC is high, that is in excess of 350 pins, or if the number of pins coming from the IC is less than 350 but the required overall package size is small (resulting in a solder ball pitch of less than 1.27 um.), the plastic flip chip structure becomes complicated and expensive. This can be traced to the multi-layer structure used to create the plastic flip chip package. This multi-layer structure results in a line density within the package of typically 2-3 mil or 50 u-75 u range. This line density is not sufficiently high for realizing the fan out from the chip I/O to the solder balls on the package within a single layer, leading to the multi-layer approach. The multi-layer approach brings with it the use of relatively thick (50 u-75 u) dielectric layers, these layers have a Coefficient of Thermal Expansion (CTE) that is considerably higher than the CTE of the laminate board on which the plastic flip chip package is mounted. To counteract this difference in CTE's the overall package must be (thermally and mechanically) balanced resulting in the use of additional material and processing steps to apply these materials, increasing the cost of the BGA package and creating a yield detractor.
Other Prior Art applications use thin film interconnect layers for chip or wire bond packaging substrates. These applications start with a laminate substrate onto which the thin film layers are deposited. For these applications, the laminate substrate is used as a base carrier substrate and provides the mechanical support. Plated Through Holes (PTH) are mechanically drilled through the laminate substrate and are used to establish connections to the backside of the substrate for solder ball attach and electrical contacts. By using thin films, high wire density and very thin dielectric layers can be realized. This approach also does not require the counter-balancing of thick layers of dielectric in order to establish dimensional stability. A disadvantage of the laminate substrate is that the process of mechanically drilling holes through the laminate substrate is time-consuming, adding cost to the process. Further, the planarity of the laminate substrate does not meet planarity requirements for the deposition of thin films. Good planarity for the surface of the laminate substrate is established by depositing dielectrics and metal layers on the initial surface of the laminate structure, steps that again add to the processing cost of the flip chip structure. Since the laminate substrate is composed using organic materials, the substrate is also not dimensionally stable resulting in warpage and dimensional variations during high temperature processing and wet chemical interactions. This results in additional processing complications and costs.
The packaging of a flip chip to a printed circuit board consists of attaching the flip chip to this board or to any other matching substrate. A flip chip is a semiconductor chip that has a pattern or array of terminals spaced around the active surface of the flip chip, the flip chip is mounted face (active surface) down onto a substrate. Electrical connectors that are provided on the active surface of the flip chip can consist of Ball Grid Arrays (BGA's) and Pin Grid Arrays (PGA's). With the BGA, an array of minute solder balls is disposed on the surface of the flip chip for attachment to the surface of the substrate. For PGA's, an array of small pins extends essentially perpendicularly from the active surface of the flip chip, such that the pins conform to a specific arrangement on a printed circuit board or other substrate for attachment. An extension of the BGA concept is the Slightly Larger than Integrated Circuit Carrier (SLICC) arrangement which is characterized by a smaller solder ball pitch and a smaller solder ball diameter than the BGA. It is clear that the solder or other conductive ball or pin arrangements of the flip chip must be a mirror image of the connecting bond pads on the printed circuit board so that precise connection can be made. The flip chip is bonded to the printed circuit board by refluxing the solder balls or pins (for the PGA) of the flip chip. The solder balls may also be replaced with a conductive polymer.
Flip chips are typically hermetically sealed to the substrate by using glob top and underfill materials between the flip chip and the substrate. Not all flip chip packages use chip back surface protection (glob top) l

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