Electrical computers and digital processing systems: support – Multiple computer communication using cryptography – Security kernel or utility
Reexamination Certificate
1998-09-11
2001-12-04
Peeso, Thomas R. (Department: 2132)
Electrical computers and digital processing systems: support
Multiple computer communication using cryptography
Security kernel or utility
C380S028000, C380S029000
Reexamination Certificate
active
06327654
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit for cryptographic process and an encryption algorithm alternating method, which are capable of achieving improvement of a security protection performance of cryptography.
2. Description of the Related Art
In recent years, according to the development of communication infrastructure such as the Internet, etc., a concern for the electronic commerce which can arrange the settlement of accounts of the money on the network is caused and the cryptographic technology is needed as the important technology. Such cryptographic technology should be employed since secrecy of the contents can be ensured by coding an amount of money, approved contents, etc. in communication even in the case that an outsider intercepts the contents of the electronic commerce in the middle of communication. Nevertheless, there has been no absolutely reliable cryptographic technology at present.
FIG. 1
is a schematic block circuit diagram showing a semiconductor integrated circuit for cryptographic process in the prior art. In the semiconductor integrated circuit for cryptographic process, the same key is employed as the locking key and the unlocking key and also the transmitter and the receiver possess commonly the same key. A basic algorithm will be explained hereinbelow.
A text input which is formed as a block of 64 bit (8 byte) is divided into two right and left 4 byte (32 bit), and then one of two 4 byte is input into a function F portion
101
. In this function F portion
101
, randomizing process is executed by using the key data, then an exclusive logical sum of randomized data and the other of 4 byte is calculated by an exclusive logical sum (EXOR, indicated by an encircled + mark)
3
, and then the exclusive logical sum is output to a succeeding function F portion
101
. In this manner, the above randomizing process is repeated in unit of 4 byte by using a function F and key information. In the end, the right and left 4 byte are synthesized to obtain an 8-byte coded text. Decoding process can be executed by carrying out the above steps sequentially in reverse order.
FIG. 2
shows a DES (Data Encryption Standard) which is employed as a standard at present. This DES is employed in the function F portion
101
in FIG.
1
. In
FIG. 2
, a unit E executes process of expanding 32 bit into 48 bit. Each of steps S
1
to S
8
denotes a table which converts 6 bit into 4 bit. In addition, a unit P is a processing portion which rearranges the bit order of 32 bit. In this way, in the DES, permutation of data is performed at the first round of the input portion and the final output portion.
Like the above, in the semiconductor integrated circuit for cryptographic process in the prior art, since an encryption algorithm is fixed, it is possible to decrypt the cryptography by virtue of full search of keys. In order to make the full search of keys impossible in practical use, a time consumed in the cryptographic process may be enhanced by increasing an amount of hard ware of the semiconductor integrated circuit for cryptographic process, e.g., increasing the round number in
FIG. 1
, etc.
However, if an amount of the hard ware of the semiconductor integrated circuit for cryptographic process is increased in order to make the decryption impossible in practical use, first there has been such a problem that an occupied area of the semiconductor integrated circuit is increased inevitably because a considerable amount of the hard ware is needed. Second, there has been another problem that it takes a lot of time to execute the process in normal use because a considerable amount of the hard ware is also needed.
SUMMARY OF THE INVENTION
The present invention has been made in light of the above circumstances and it is an object of the present invention to achieve extensive improvement of a security protection performance of cryptography.
It is another object of the present invention to execute cryptographic process at high speed.
It is still another object of the present invention to achieve reduction in a packaging area of a semiconductor integrated circuit for cryptographic process.
In order to achieve the above objects, there have been problems that, even if the security protection performance of the cryptography is improved by increasing an amount of the hard ware like the prior art, the packaging area is increased enormously and also the processing speed is reduced because of a large quantity of process. Therefore, inventors of the present invention have thought about how to solve the above problems by using any epoch-making approach.
In recent years, the inventors of the present invention have found out that, if the semiconductor integrated circuit for cryptographic process is so constructed that the encryption algorithm per se can be varied by using a reconfigurable semiconductor integrated circuit, the above problems can be solved at one breath. This is because such reconfigurable semiconductor integrated circuit is highly flexible in employment because its circuit configuration is alterable according to an external input signal. As the result of the carefully pursued study, the inventors of the present invention have been implemented the inventions set forth in the following.
As a preferred embodiment of the present invention, there is provided a semiconductor integrated circuit for cryptographic process, for executing the cryptographic process of input data based on key data, comprising:
a randomizing means for executing randomizing process of the input data based on configuration information to identify an algorithm in randomizing process.
In the above semiconductor integrated circuit, the randomizing means which can alternate the randomizing process based on the configuration information is provided. Hence, extreme improvement of the security protection performance of the cryptography and high speed cryptographic process can be achieved while reducing a packaging area.
As another preferred embodiment of the present invention, there is provided a semiconductor integrated circuit for cryptographic process, for dividing input data into a plurality of data and executing cryptographic process of input data based on key data, comprising:
a randomizing means for randomizing first input data which is one of two divided parts of the input data, based on configuration information to identify an algorithm in randomizing process;
a function F portion for receiving data which have been subjected to the randomizing process and then applying the cryptographic process to the data; and
an exclusive logical sum circuit for receiving second input data which is other of two divided parts of the input data and output data from the function F portion and then outputting an exclusive logical sum of the second input data and the output data.
In the above semiconductor integrated circuit, the randomizing means may be provided in the circuit explained in the prior art and shown in FIG.
1
. Therefore, the present invention can be implemented by adding the randomizing means to the semiconductor integrated circuit for cryptographic process employed in the prior art. Also, as shown in
FIG.3
, if several rounds of the above configuration of the present invention are provided, the security protection performance of the cryptography can be improved much more.
As still another preferred embodiment of the present invention, there is provided a semiconductor integrated circuit for cryptographic process, for dividing input data into a plurality of data and executing cryptographic process of input data based on key data, comprising:
a randomizing means for applying randomizing process to the input data based on configuration information to identify an algorithm in the randomizing process;
a function F portion for receiving data which have been subjected to the randomizing process and then applying the cryptographic process to the data;
an exclusive logical sum circuit for receiving first input data which is one of two divid
Endo Naoki
Fujii Hiroshige
Kato Takehisa
Masuda Atsushi
Nishi Hiroaki
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Peeso Thomas R.
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