Digital receiver with polyphase structure

Details Digital receiver with polyphase structure Digital receiver with polyphase structure

1998-08-31

2001-11-27

Deppe, Betsy L. (Department: 2634)

Pulse or digital communications

Receivers

Angle modulation

C375S329000

Reexamination Certificate

active

06324222

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital receiver, and more particularly, to an apparatus for extracting specific channel data from multi-channel discrete time data.
2. Description of the Related Art
A digital receiver receives discrete time data converted from a multi-channel analog signal through an analog-to-digital (A/D) converter and extracts desired channel data therefrom.
As illustrated in
FIG. 1
, a conventional digital receiver includes multipliers
10
and
12
, a local oscillator
14
, and a low pass filter (LPF)
16
. The LPF
16
may be a decimating low pass FIR (Finite Impulse Response) filter.
In operation, an input signal S[n] applied to an input terminal of the digital receiver is a digital signal consisting of an I channel component and a Q channel component. An example of the input signal S[n] can be given by:
S[n]=I[n]
·cos
W
s
n+Q[n]
·sin
W
s
n
  (1)
where I[n]·cos W
s
n and I[n]·sin W
s
n denote the I channel component and the Q channel component, respectively.
The input signal S[n] is multiplied through the multipliers
10
and
12
by intermediate frequency signals sin[W
s
n] and cos[W
s
n], respectively. The multipliers
10
,
12
generate both a baseband signal and a high frequency signal. The intermediate frequency signals cos[W
s
n] and sin[W
s
n] are produced from the local oscillator
14
. The baseband signal and the high frequency signal generated from the multipliers
10
and
12
are supplied to the LPF
16
which removes the high frequency component and passes only the baseband signal that the user desires to receive.
In the above structure of the digital receiver, since the input signal S[n] is a sampled digitally converted signal, the multipliers
10
and
12
should have the same data processing rate as a sampling rate of the input signal S[n]. If the sampling rate of the input signal S[n] is high, then multipliers
10
and
12
must be high speed devices so as to process the input signal S[n] with a high sampling rate. This presents a disadvantage in that if the digital receiver is achieved by using a commercially available DSP (Digital Signal Processor) chip, a high-speed multiplier must be provided in the DSP chip. Even though such multipliers can be achieved on an integrated circuit chip, the complicated multiplier has an adverse effect on other processors, and thus a single DSP chip cannot be used.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a digital receiver which can reduce a processing load by arranging a multiplier at the rear thereof so as to allow operation at a lower data processing rate.
To achieve the above object, a digital receiver having a polyphase structure is provided by the present invention which has an input terminal for receiving a digital input signal converted by a given sampling rate and includes: a plurality of delays for sequentially delaying the input signal or an output of the preceding delay; a first branch having a first down-sampler for lowering a sampling rate of the input signal within the possible range according to a unique characteristic of the input signal, a plurality of down-samplers for lowering a sampling rate of the input signal within the possible range according to a unique characteristic of the input signal, a first filter for filtering only a signal of a desired channel from a signal received from the first down-sampler, a plurality of filters for filtering only signals of a desired channel from signals received from the plurality of down-samplers, a first adder for adding an output of the first filter to an output of the following filter, and a plurality of adders for respectively adding an output of the preceding adder to the corresponding filter; a second branch having the same construction as the first branch, the first and second branch being symmetric on the basis of the delays; a first multiplier for multiplying an output of the last adder of the first branch by e
−jWsMn.
, a second multiplier for multiplying an output of the last adder of the second branch by e
jWsMn
; a second adder for adding outputs of the first and second multipliers to each other to generate a signal corresponding to an I channel; a third adder for generating a difference between outputs of the first and second multipliers; and a third multiplier for multiplying an output of the third adder by a complex number to generate a signal corresponding to a Q channel.


REFERENCES:
patent: 4893316 (1990-01-01), Janc et al.
patent: 4910752 (1990-03-01), Yester, Jr. et al.
patent: 5521944 (1996-05-01), Hegeler et al.
patent: 5715259 (1998-02-01), Lee et al.
patent: 5715529 (1998-02-01), Kianush et al.
patent: 5787125 (1998-07-01), Mittel
patent: 6215828 (2001-04-01), Signell et al.

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