Method of plasma etching dielectric materials

Details Method of plasma etching dielectric materials Method of plasma etching dielectric materials

1998-09-30

2001-10-02

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S714000, C438S723000

Reexamination Certificate

active

06297163

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an improved method for plasma etching dielectric materials such as silicon oxide in the fabrication of integrated circuits.
BACKGROUND OF THE INVENTION
A common requirement in integrated circuit fabrication is the etching of openings such as contacts and vias in dielectric materials. The dielectric materials include doped silicon oxide such as fluorinated silicon oxide (FSG), undoped silicon oxide such as silicon dioxide, silicate glasses such as boron phosphate silicate glass (BPSG) and phosphate silicate glass (PSG), doped or undoped thermally grown silicon oxide, doped or undoped TEOS deposited silicon oxide, etc. The dielectric dopants include boron, phosphorus and/or arsenic. The dielectric can overlie a conductive or semiconductive layer such as polycrystalline silicon, metals such as aluminum, copper, titanium, tungsten, molybdenum or alloys thereof, nitrides such as titanium nitride, metal silicides such as titanium silicide, cobalt silicide, tungsten silicide, molydenum silicide, etc.
Various plasma etching techniques for etching openings in silicon oxide are disclosed in U.S. Pat. Nos. 5,013,398; 5,013,400; 5,021,121; 5,022,958; 5,269,879; 5,529,657; 5,595,627; 5,611,888; and 5,780,338. The plasma etching can be carried out in medium density reactors such as the parallel plate plasma reactor chambers described in the '398 patent or the triode type reactors described in the '400 patent or in high density reactors such as the inductive coupled reactors described in the '657 patent. Etching gas chemistries include the oxygen-free, Ar, CHF
3
and optional CF
4
gas mixture described in the '121 and '958 patents, the oxygen-free, fluorine-containing and nitrogen gas mixture described in the '879 patent, the C
4
F
8
and CO gas mixture described in the '627 patent, the oxygen and CF
4
gas mixture described in the '400 patent, the oxygen, CF
4
and CH
4
gas mixture described in the '657 patent, and the Freon and neon gas mixture described in the '888 patent.
U.S. Pat. No. 5,736,457 describes single and dual “damascene” metallization processes. In the “single damascene” approach, vias and conductors are formed in separate steps wherein a metallization pattern for either conductors or vias is etched into a dielectric layer, a metal layer is filled into the etched grooves or via holes in the dielectric layer, and the excess metal is removed by chemical mechanical planarization (CMP) or by an etch back process. In the “dual damascene” approach, the metallization patterns for the vias and conductors are etched in a dielectric layer and the etched grooves and via openings are filled with metal in a single metal filling and excess metal removal process.
Medium density plasma reactors operate at higher chamber pressures and dissociate etching gas chemistries to a lesser extent than high density plasma reactors. For instance, in medium density plasma reactors, etching gases such as C
4
F
8
dissociate in stages as follows: C
4
F
8
→C
2
F
8
→CF
2
→CF+F. Due to such gradual dissociation, it is possible to achieve a high etch rate of a dielectric layer and a low etch rate of an overlying layer such as a photoresist or underlayer such as an etch stop layer. The ratio of such etch rates is referred to as the “etch selectivity ratio” and the high selectivity ratios obtainable in medium density plasma reactors promote complete etching of contacts, vias and conductor patterns. In contrast, in high density reactors, the instantaneous dissociation of etching gases can lead to low selectivity ratios due to the higher etch rates of the masking layer and etch stop layers. For example, in high density plasma reactors, C
4
F
8
dissociates directly to free F and the high content of free F causes such rapid etching of the masking and/or etch stop layers that the etch selectivity ratio is unacceptably low.
As device geometries become smaller and smaller, the need for high etch selectivity ratios is even greater in order to achieve plasma etching of deep and narrow openings in dielectric layers such as silicon oxide. Accordingly, there is a need in the art for a high density plasma etching technique which provides high etch selectivity ratios and/or which achieves deep and narrow openings. Further, it would be highly desirable to achieve such opening geometries without bowing of the sidewalls of the openings.
SUMMARY OF THE INVENTION
The invention provides a process for plasma etching a dielectric layer, comprising the steps of introducing a semiconductor substrate into a high density plasma etching reactor, the semiconductor substrate including a masking layer and an electrically conductive or semiconductive layer underlying a dielectric layer. The dielectric layer can be etched in a single step to expose the electrically conductive or semiconductive layer and provide openings extending through the dielectric layer to the electrical conductive or semiconductive layer. The etching is performed by exposing the dielectric layer to an etching gas in an ionized state in the high density plasma etching reactor, the etching gas including fluorocarbon reactant and carbon monoxide and an optional inert carrier gas. In the process, the high density plasma causes the fluorocarbon to instantaneously disassociate into free F and free C and the carbon monoxide is present in an amount effective to increase selectivity of the etch rate of the dielectric layer to the etch rate of the masking layer.
According to one aspect of the invention, the dielectric layer comprises silicon oxide such as doped or undoped silicon dioxide, BPSG, PSG, TEOS, or thermal silicon oxide and the openings comprise grooves corresponding to a conductor pattern, via openings or contact openings. According to another aspect of the invention, the openings can be etched so as to have an aspect ratio of at least 3:1. The etching gas can include a hydrogen-containing and/or a hydrogen-free fluorocarbon reactant represented by C
x
F
y
H
z
wherein x is at least 1, y is at least 1 and z is equal to or greater than 0. For example, the fluorocarbon reactant can be selected from the group of CF
4
, C
4
F
8
, C
2
F
6
, C
3
F
6
, C
3
F
8
, C
5
F
8
, CH
3
F, C
2
HF
5
and/or CH
2
F
2
. The electrically conductive or semiconductive layer can comprise a metal-containing layer selected from the group consisting of Al, Al alloys, Cu, Cu alloys, Ti, Ti alloys, doped or undoped polycrystalline or single crystal silicon, TiN, TiW, Mo, silicides of Ti, W, Co and/or Mo, etc.
The process of the invention can etch openings which are 0.30 &mgr;m, especially 0.25 &mgr;m or smaller sized openings with depths of at least 1.8 &mgr;m using a fluorocarbon reactant which comprises C
x
F
y
H
z
wherein x is 1 to 5, y is 1 to 8 and z is 0 to 3. As an example, the fluorocarbon reactant can comprise one or more gases selected from C
2
HF
5
, CH
2
F
2
, C
2
F
6
, C
3
F
6
, C
4
F
8
and mixtures thereof. The optional carrier gas can be selected from the group consisting of Ar, He, Ne, Kr, Xe or mixtures thereof. The CO can be supplied to the plasma reactor at a flow rate of 25 to 250 sccm, the fluorocarbon can be supplied to the plasma reactor at a flow rate of 5 to 100 sccm, and the optional carrier gas can be supplied to the plasma reactor at a flow rate of 10 to 300 sccm. As an example, CO, fluorocarbon, and Ar can be supplied to the plasma reactor at flow rates of 50 to 200 sccm, 40 to 70 sccm and 50 to 150 sccm, respectively. During the etching step, the high density plasma reactor is preferably maintained at a vacuum pressure of 10 mTorr or below. The etching step can be followed by filling the openings with metal. The method of the invention can also include steps of forming a photoresist layer on the dielectric layer, patterning the photoresist layer to form a plurality of openings and the etching step forms a metallization pattern of conductor lines, via or contact openings in the dielectric layer. With the process, openings can be formed with

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