Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1999-10-22
2001-10-02
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S678000
Reexamination Certificate
active
06297553
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a process for producing the same. More specifically, the invention relates to a semiconductor device of a small size, such as a chip-size package (CSP) or the like, which makes it possible to easily increase the number of the pins yet reduce the cost of production, and to a process for producing the same.
2. Description of the Related Art
The chip-size package (CSP) is a semiconductor device in which external connection terminals such as solder balls are formed on a mounting surface that is formed nearly the same size as the semiconductor chip. The semiconductor device is mounted on a mother board by using the external connection terminals.
In the chip-size package (CSP) as shown in
FIG. 1
, the electrode terminals
102
formed near the peripheral edges of the semiconductor chip
100
are electrically connected by wiring patterns
104
including lands
106
on which will be mounted the external connection terminals that are mounted on the mother board.
The wiring patterns
104
can be formed on a passivation film of the semiconductor chip
100
, or can be formed by joining a wiring pattern film on which wiring patterns
104
are formed onto the passivation film of the semiconductor chip
100
.
When a plurality of lands
106
are formed on the electrode terminal carrying surface of the semiconductor chip
100
, space must be maintained for arranging outgoing lines among the neighboring lands. However, the terminal lands
106
to which are connected external connection terminals for mounting on the mother board must have a diameter of about 300 &mgr;m. Therefore, a limitation is imposed on the number of the terminal lands
106
formed on the electrode terminal carrying surface of the semiconductor chip.
In modern semiconductor devices, on the other hand, semiconductor chips are being fabricated in ever smaller sizes resulting in an increase in the density for forming the external connection terminals. As described above, however, a limitation is imposed on the number of the terminal lands when the terminal lands for mounting the external connection terminals are formed on the electrode terminal carrying surface of the semiconductor chip, making it difficult to meet the demand for realizing the semiconductor chips in small sizes.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a semiconductor device capable of easily meeting the demand for realizing the semiconductor chips in small sizes, and a process for producing the same.
In order to achieve the object, the present inventors have attempted to form the terminal lands for mounting the external connection terminals on an interposing substrate formed separately from the semiconductor chip, and to electrically connect the interposing substrate to the semiconductor chip using connection bumps smaller than the external connection terminals. As a result, the inventors have learned that the connection lands can be formed on the electrode terminal carrying surface of the semiconductor chip, the connection lands having a diameter smaller than that of the terminal lands for mounting the external connection terminals.
Further, vias for electrically connecting together the conductor wiring patterns formed on both surfaces of the interposing substrate, are formed by filling the recesses with a metal by plating, the recesses penetrating through the insulating material of the interposing substrate in such a manner that the back surface of the conductor wiring pattern on one surface of the insulating material and on the side of the insulating material is exposed on the bottom surface of the recess. Thus, very fine vias are formed and the connection lands are formed having a further decreased diameter on the interposing substrate. This makes it possible to form the connection lands having a further decreased diameter on the electrode carrying surface of the semiconductor chip connected, via connection bumps, to the connection lands of the interposing substrate and, hence, to fully meet the demand for realizing the semiconductor chips in small sizes. The inventors have thus arrived at the present invention.
According to the present invention, there is provided a semiconductor device comprising:
a semiconductor chip having an electrode terminal carrying surface on which electrode terminals and conductor lands electrically connected to the electrode terminals are formed;
an interposing substrate of an insulating material having a front surface and a back surface and disposed with the front surface facing the electrode terminal carrying surface of the semiconductor chip, in which a conductor wiring pattern including conductor pads is formed on the front surface, a conductor wiring pattern including conductor lands is formed on the back surface, external connection terminals are formed on the conductor lands on the back surface, and conductor vias composed of a plated metal filling viaholes extending through the interposing substrate electrically connect the conductor wiring pattern on the front surface and the conductor wiring pattern on the back surface; and
bumps electrically connecting the conductor lands of the semiconductor chip to the conductor pads of the interposing substrate.
In the semiconductor device according to the present invention, the conductor wiring pattern on the back surface is advantageously adhered to the back surface by a thermoplastic adhesive agent layer intervening therebetween to facilitate production of the device.
According to the present invention, there is also provided a process of producing a semiconductor device, comprising the steps of:
providing an insulating material having a front surface coated with a metal foil bonded thereto and a back surface coated with a thermoplastic adhesive agent layer formed thereon;
forming recesses extending through the insulating material, the recesses having a bottom defined by the metal foil at the front surface and an opening at the back surface;
filling the recesses with a metal by electrolytic plating using the metal foil as a current supply path to form conductor vias extending through the insulating material;
adhering a metal foil to the back surface of the insulating material with the thermoplastic adhesive agent layer;
patterning the metal foils on the front surface and the back surface to form conductor wiring patterns on the front surface and the back surface, respectively, thereby forming an interposing substrate having the front surface on which a conductor wiring pattern including conductor pads for connection to conductor lands on an electrode terminal carrying surface of a semiconductor chip is formed and having the back surface on which a conductor wiring pattern including conductor lands for external connection terminals is formed, the conductor wiring patterns being electrically connected to each other through the conductor vias;
bonding and electrically connecting the conductor lands of the semiconductor chip to the conductor pads of the interposing substrate by bumps; and
forming external connection terminals on the conductor lands of the interposing substrate.
In the process according to the present invention, the steps subsequent to the step of patterning the metal foils may be replaced by the following steps:
using, instead of the semiconductor chip, a semiconductor wafer including plural semiconductor chip regions each corresponding to the semiconductor chip and having conductor lands corresponding to those of the semiconductor chip;
forming external connection terminals on the conductor lands of the interposing substrate; and
cutting, before or after the step of forming external connection terminals, the semiconductor wafer and the interposing substrate, which have been bonded together, at positions between the semiconductor chip regions.
According to the process for producing a semiconductor device of the present invention, recesses are formed by laser beam machining so as to penetrate through the insulating mater
Horiuchi Michio
Imai Kazunari
Nelms David
Nhu David
Shinko Electric Industries Co., Ltd
Staas & Halsey , LLP
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