Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-11-10
2001-11-13
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S702000, C257S401000
Reexamination Certificate
active
06316349
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices, and more particularly to a method for forming contacts of semiconductor devices, in which an oxidized silicon-rich nitride film is used as an etch barrier film in a self-aligned contact (SAC) process conducted using the etch barrier film, thereby being capable of avoiding a degradation in the quality of devices finally produced due to a short circuit of conductive lines, an etching stop caused by a reduced process margin, and stress occurring during the SAC process, so as to achieve an improvement in a yield process and an improved reliability in the operation of the devices.
2. Description of the Prior Art
The recent trend to fabricate highly integrated semiconductor devices has been greatly affected by the development of techniques of forming patterns having a micro dimension. In other words, in order to fabricate highly integrated semiconductor devices, it is necessary to form photoresist film patterns having a micro dimension. Such photoresist film patterns are widely used as masks for carrying out an etch process or ion implantation process in the fabrication of semiconductor devices.
Although the resolution of such a photoresist film pattern is greatly affected by the material of the photoresist film and the bondability of the photoresist film to a substrate, on which the photoresist film is formed, it is basically proportional to the wavelength of light emitted from a light source used in a stepper and a process constant used while being inversely proportional to the numerical aperture of the stepper. That is, the resolution can be expressed by the following equation:
R=k×8/NA
where, R represents a resolution, k represents a process constant, 8 represents the wavelength of light emitted from a light source used in a stepper, and NA represents the numerical aperture of the stepper.
In order to obtain an improvement in the resolution of the stepper, it is necessary to use a light source having a reduced wavelength. For example, G-line steppers using a wavelength of 436 nm and i-line steppers using a wavelength of 365 nm are limited in terms of resolution to about 0.7 m and about 0.5 m for line/space patterns. In order to form micro patterns having a dimension of less than 0.5 m, it is necessary to use a stepper using a light source having a wavelength shorter than those of G or i-line steppers. Such a light source may be a deep ultraviolet (DUV) source such as a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm.
In addition to attempts to improve steppers as mentioned above, improvements in processes have also been made in order to improve a limitation in resolution. For example, an use of a phase shift mask as a photo mask has been proposed. In addition, a contrast enhancement layer (CEL) method has been developed in which a separate thin film capable of achieving an improvement in an image contrast is formed on a wafer. A tri-layer resister (TLR) method has also been proposed in which an intermediate layer made of, for example, spin on glass (SOG), is interposed between two photoresist films. Also, a sililation method has been proposed in which silicon is selectively implanted in an upper portion of a photoresist film.
Meanwhile, contact holes, which are adapted to connect upper and lower conductive lines to each other, exhibit a high design rule, as compared to line/space patterns. For an increased integration degree of semiconductor devices, such contact holes have a reduced size and a reduced space from peripheral lines. Furthermore, an increase in an aspect ratio is involved. The aspect ratio represents the depth-to-diameter ratio of a contact hole.
For this reason, where a highly integrated semiconductor device having a multi-layer conductive line structure is to be fabricated, an accurate and strict alignment among masks is required in the fabrication of the semiconductor device. This results in a reduction in a margin process.
Masks for the formation of such contact holes are formed, taking into consideration a misalignment tolerance involved in the process of aligning those masks with one another, a lens distortion involved in a light exposure process, a critical dimension variation involved in the process of forming those mask and conducting a photolithography, and a registration among those masks, in order to maintain a desired space between adjacent contact holes.
For such a contact hole formation method, there have been proposed a direct etch method, a method using side-wall spacers, and an SAC (self align contact) method.
The direct etch method and the method using side-wall spacers exhibit a limitation involved in the fabrication of highly integrated semiconductor devices because they cannot be applied to the fabrication of semiconductor devices involving a design rule of 0.3 m or less in accordance with current techniques.
The SAC method has been proposed in order to overcome a limitation involved in a lithography used in the formation of contact holes. Known SAC methods are classified in accordance with an etch barrier film used. For such an etch barrier film, a polysilicon film, a nitride film, and an oxidized nitride film. A preferred one is an SAC method using a nitride film as an etch barrier film.
Now, various examples of conventional methods for forming self-aligned contacts of semiconductor devices will be described in detail.
In accordance with one example of a conventional method for forming self-aligned contacts of semiconductor devices, a desired underlayer structure is formed on a semiconductor substrate. The underlayer structure may include a device isolation oxide film, and metal oxide semiconductor field effect transistors (MOSFETs) each including a gate electrode and a source/drain region overlapping with a gate oxide film and a mask oxide film pattern, respectively. Over the entire exposed upper surface of the resulting structure, an etch barrier film and an interlayer insulating film made of an oxide material are then sequentially formed.
Thereafter, a photoresist film pattern is formed on the resulting structure in order to expose portions of the interlayer insulating film corresponding to regions where contacts for charge storage electrodes and bit lines, etc. are to be formed, respectively.
The interlayer insulating film is then dry-etched at its exposed portions not covered with the photoresist film pattern, thereby causing the etch barrier film to be partially exposed. The etch barrier film is subsequently etched at its exposed portions, thereby forming contact holes.
Where the etch barrier film is made of polysilicon, the formation thereof may be carried out using a method, in which the etch barrier film is completely formed over the entire surface of the semiconductor substrate, or a method in which the etch barrier film is formed in the form of pads on portions of the semiconductor substrate corresponding to the contact hole forming regions, respectively.
Since polysilicon, which exhibits an etch mechanism different from that of oxide, is used to form the etch barrier film, it is possible to obtain a high etch selectivity difference with regard to the oxide films disposed therebeneath.
However, the poly barrier SAC formation method exhibits a degradation in reliability in regard to the insulation among contact holes. On the other hand, the pad formation method involves a damage of the silicon substrate occurring when the contact pads are misaligned from the silicon substrate.
In order to solve the above-mentioned problems, formation of spacers or expansion of contact pads has been proposed. However, these methods involve a problem in that they cannot realize a design rule of 0.18 m or less.
The SAC method using a nitride film as an etch barrier film (poly barrier SAC) is known as a method capable of solving the above mentioned problems.
In accordance with this SAC method, the interlayer insulating film is dry-etched under the condition in which th
Kim Jeong Ho
Kim Jin Woong
Kim Si Bum
Ku Ja Chun
Oh Su Jin
Hyundai Electronics Industries Co,. Ltd.
Jacobson & Holman PLLC
Le Dung A
Nelms David
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