Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-01-08
2001-11-06
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S299000, C438S303000, C438S583000, C438S592000, C438S682000, C438S685000
Reexamination Certificate
active
06313032
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a salicide transistor, a semiconductor storage, and a semiconductor device, and more specifically to a method for manufacturing a salicide transistor that uses cobalt silicide as the salicide, a semiconductor storage such as a DRAM that uses the above salicide transistor, and a semiconductor device formed by packaging the above semiconductor storage and a logic device.
2. Description of Related Art
In order to increase the operating speed of an LSI, it is essential to decrease the parasitic resistance of transistors that is an element configuring the LSI. For this reason, a silicide has been used for decreasing the resistance of the diffusion region of a transistor. When a silicide is used, there are the following two technical problems:
(1) Increase in the sheet resistance of the silicide formed on the diffusion region of a width of about 0.3 &mgr;m or less (known as increase in narrow-line resistance), and
(2) Occurrence of P-N-junction leakage in the silicide formed on a shallow P-N junction in the source/drain region.
Although the formation of a thick silicide layer is considered as the solution for the above problem (1), this is not the best method because this may cause the junction leakage of a shallow P-N junction. If the heat-treatment step is unavoidable for the formation of a film between contact layers or the formation of a capacitor structure, the silicide is easily degraded by the heat treatment, for example, the resistance of the silicide is easily increased by aggregation. The lowering of the heat-treatment temperature is considered to solve this problem. Although the resistance of the silicide is lowered by merely lowering the heat-treatment temperature, the desired element structure cannot be formed. For the above reason, the control of increase in the narrow-line resistance of the silicide becomes extremely difficult.
Although the formation of a thin silicide layer is considered for solving the above problem (2), this is not the best method because the sheet resistance is increased by decreasing the thickness of the silicide, and the effect of decreasing parasitic resistance cannot be obtained. The above-described problems (1) and (2) are in a trade-off relationship with each other.
Furthermore, with the reduction of the element size, the source/drain P-N junction becomes shallower. Since even the local protrusion of a silicide film may cause P-N-junction leakage to occur, the techniques for improving the uniformity of the film thickness, and for eliminating the irregularity of the silicide-silicon interface have been demanded. Since the morphology of silicide is affected not only by the process conditions of silicide formation, but also by the conditions of preceding and following processes, the optimization of the total process becomes essential.
FIGS.
3
(A)-
3
(E) show the manufacturing flow of a conventional salicide transistor exemplified by the formation on an NMOS. In
FIG. 3
, reference numeral
100
denotes a P-type silicon (Si) substrate,
102
denotes a P well,
101
denotes an element separating oxide film formed on the P well
102
,
103
denotes a gate oxide film,
104
denotes an N-type polysilicon (poly-Si) gait electrode formed on the gate oxide film
103
,
105
denotes a WSi gate electrode formed on the N-type poly-Si gate electrode
104
,
106
denotes an oxide film formed on the WSi gate electrode
105
,
108
denotes a side wall that covers the side of the WSi gate electrode
105
and the like,
107
denotes an N-type LDD (lightly doped drain) region, and
116
denotes a high-concentration implanted layer (high-concentration diffusion layer) region.
As FIG.
3
(A) shows, the formation of element separating oxide films
101
, the implantation of P wells
102
, the formation of gate electrodes
105
and the like, the formation of N
−
-type LDD region
107
, and the formation of side walls
108
are performed by known methods, and an impurity is implanted into the region
109
where the high-concentration diffusion layer of source/drain regions and the like is formed. An opening is made in only the implantation region by the patterning of a photoresist (not shown), 4×10 cm
−2
of As
+
ions are implanted under the condition of an energy of 30 keV, and 1×10 cm
−2
of P
+
ions are implanted under the condition of an energy of 40 keV.
Prior to salicide forming process, a protecting film is formed and patterned to protect regions from the silicying reaction where silicide is not to be formed. In FIG.
3
(B), reference numeral
109
denotes a high-concentration source/drain region formed by the above-described impurity implantation. As FIG.
3
(B) shows, a TEOS oxide film
115
of a thickness of 50 nm is formed as the protecting film from the silicfying reaction using the reduced pressure CVD method at a film formation temperature of 670° C. Thereafter, the resist is patterned using a photolithography process to open a desired portion for forming silicide. Next, the oxide film is removed from the opened portion of the resist using a diluted HF aqueous solution, and then the photoresist is removed using ashing by oxygen plasma.
As FIG.
3
(C) shows, cobalt silicide (CoSi
2
)
110
is formed only in the region where Si is exposed using a salicide flow. First, the oxide film is removed using a diluted HF aqueous solution from the Si surface of the region
109
where the high-concentration diffusion layer is to be formed. Next, lump annealing is performed in an N
2
atmosphere at 430° C. for 90 seconds to allow Co to react with Si to form a Co—Si compound, and then free Co is removed using a nitric acid/acetic acid/phosphoric acid mixed aqueous solution. Thereafter, lump annealing is performed in an N
2
atmosphere at 850° C. for 60 seconds.
As FIG.
3
(D) shows, an interlayer insulating film is formed. A thin Si
3
N
4
film
111
of a thickness of 10 nm is formed using the reduced pressure CVD method at a film forming temperature of 700° C., on which a BPSG (borophosphosilicate glass) film
112
of a thickness of 60 nm is formed using the normal pressure CVD method at a film forming temperature of 350° C. Thereafter, heat treatment is performed for the reflow of the BPSG film
112
in the purpose of improving the embedding property of the interlayer film between gate electrodes
105
or the like, and improving surface flatness. The reflow is performed in an H
2
/O
2
atmosphere of an atmospheric pressure at 800° C. for 20 minutes. This heat treatment also recovers the crystallinity of the implanted layer
109
in the diffusion region, and activates the added impurity.
Thereafter, as FIG.
3
(E) shows, a barrier metal (TiN)
116
and a contact plug (W plug)
113
structures are formed after opening the contact holes, and wiring (aluminum wiring)
114
is formed. When a device having a DRAM and a logic device is formed, the memory-cell capacitor structure is also formed.
In conventional methods for manufacturing a salicide transistor, as described above, the heat treatment for recovering the crystallinity of the source/drain implanted layer
109
and activating the added impurity was also used as the heat treatment for the reflow of the interlayer film. Since silicide
110
was formed on the surface of Si having poor crystallinity after source/drain implanting, the morphology of the silicide
110
was poor, and caused the narrow-line resistance to increase and junction leakage to occur. Since the silicide
110
was formed at a temperature as high as 850° C., the heat treatment in the total process was also excessive. Moreover, since the heat treatment for the reflow of the interlayer film or the like was added, the distribution of the source/drain impurity expanded due to diffusion, there were the problems of increase in off-leakage due to the short-channel effect of the transistor, and decrease in current driving capability due to increase in parasitic resistance.
As described above, since the
Hachisuka Atsushi
Yamada Keiichi
Le Vu A.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Owens Beth E.
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