Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-09-09
2001-05-08
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S003000, C711S135000, C711S165000, C710S120000, C710S120000
Reexamination Certificate
active
06230241
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to digital data processing and data communications systems. More specifically, the invention relates to the transfer of data between a source and a destination memory within such systems.
BACKGROUND OF THE INVENTION
The internal architecture of a typical digital data processing system includes a system bus for coupling input/output (I/O) devices, such as data ports, terminals, disks, and so forth to/from a central processing unit (CPU) and a memory system. The CPU is responsible for executing programs which control and schedule data transfers over the system bus between the various I/O devices. The memory system is usually segmented into a main memory segment and various I/O memory segments operatively associated with each respective I/O device coupled to the system bus. The main memory stores data and programs that execute on the CPU and each I/O memory buffers data that is transferred to and/or from the I/O device with which the I/O memory is associated. Various mechanisms are used to transfer data between an I/O memory associated with one I/O device to an I/O memory associated with another I/O device.
One such data transfer mechanism is programmed input/output (PIO). PIO is a program executing on the CPU which uses the CPU as the data transfer engine. A PIO data transfer occurs when a router used to route data over a computer network receives data from the network at a source data port device. As the data arrives, the source data port device buffers the data in its associated I/O memory. After the CPU in the router determines the destination for the data, the CPU performs a transfer of the data to a destination data port device. To perform the transfer, the CPU transfers one unit of data at a time from an I/O memory location in the I/O memory associated with the source data port device to an I/O memory location in the I/O memory associated with the destination data port device. This process repeats itself in a PIO-loop until all of the data has been transferred from the source to the destination data port device. The data remains buffered in the I/O memory of the destination data port device until this device can transmit the data out of the router back onto the computer network.
Another mechanism used to transfer data between I/O devices is Direct Memory Access (DMA). DMA uses a specialized microprocessor called a DMA controller. The DMA controller is coupled to the system bus and to the memory system and operates in conjunction with the CPU to transfer data. Once the CPU determines the length and the source and destination locations of the data to be transferred, the CPU configures the DMA controller with this information. Once configured, the DMA controller carries out the memory transfers on the designated block of data without further assistance from the CPU. Data transfers occur by beginning at the start of a source location or block of data and proceed until the specified length of data has been transferred to the destination location. The use of DMA reduces the processing power required by the CPU to perform memory transfers between I/O devices. As such, the CPU can be used for other processing tasks while the data transfer takes place.
In high speed DMA applications, a data transfer technique known as “bursting” is employed. Bursting is a memory access protocol in which a single memory address request (i.e. a single read) is passed to an I/O memory and in response, a predetermined number of memory units are returned. Bursting avoids the need to pass an address for every data unit requested and thus reduces the overhead on the system bus for data transfers. A typical DMA controller that uses bursting can transfer four words of memory using just five cycles. The first cycle specifies the source address from the DMA controller to the I/O memory, and the remaining four cycles are used to return the contents of four units of I/O memory in response to the initial request. Without bursting, at least eight cycles would be needed to transfer four memory units (i.e., one request and one response per unit).
In certain computerized data processing systems, particularly those with high speed CPU's, another memory system called a cache memory or just a “cache” is coupled to the system bus in addition to the aforementioned memory systems. The cache is usually much smaller in capacity than the other memory systems but has very high speed access capabilities. Cache memory is often built into the circuitry of a microprocessor. The built-in nature of cache memory eliminates the need to arbitrate for the system bus when the CPU needs to access memory. Cache memory thus increases processing speeds attainable by the CPU by removing memory and system bus access performance bottlenecks.
Cache memory is used to store data that is frequently and/or repetitively accessed during CPU operation. This is called “caching” the data. For instance, as a router operates, a routing table must be consulted for each data packet that passes through a router to determine where to send the data packet next. The cache can be used to store frequently accessed portions of the routing table. By caching the routing table, the CPU is provided with high speed access to frequently needed routing information and can route packets faster than if access to the primary memory system were required.
Cache memory is often maintained as a mirror image of a portion of main memory and is used with the bursting technique noted above to be updated quickly. That is, the cache memory can have portions which are “mapped” to main memory so that respective portions of the cache and main memory are always more or less in synchronicity with each other. Bursting also allows main memory to be quickly updated with changes made in corresponding mapped portions of the cache. In such cases, high speed reads and writes are performed by the CPU directly to data in the cache, and the corresponding mapped address locations in main memory are later updated by “flushing” the cache to main memory during periods of time when the CPU is idle. In this manner, the cache serves as a high speed buffer for frequently accessed data, and when this data changes, the contents of the cache are “flushed” back to main memory.
Various commercially available microprocessors incorporate CPU logic processing circuitry along with a cache memory unit and a DMA controller all within a single integrated circuit. An example is the Motorola MPC860 PowerPC microcontroller manufactured by Motorola, Inc. of Scottsdale, Ariz. The MPC860 chip provides, among other things, a powerful 32-bit CPU microprocessor in conjunction with a bursting DMA controller and a bursting cache memory system.
SUMMARY OF THE INVENTION
This invention provides an apparatus and method for a computing device using a microprocessor that provides fast and efficient use of system resources for transferring data between two I/O devices. In a preferred embodiment, the microprocessor in a computing device to which this invention may be applied is the Motorola MPC860 PowerPC chip (hereinafter the MPC860 chip). The invention, however, is not limited to computing devices using this chip. The MPC860 chip can be used as the main CPU for controlling data transfers within data processing and computing systems such as routers, switches, hubs, bridges, modem banks, and other such data communications and data processing devices. Such devices using the data transfer concepts described herein are considered to be within the scope of this invention.
We have found that certain inefficiencies exist in current data transfer schemes. Notably, the CPU portion of the MPC860 chip can configure the on-board DMA controller to perform DMA transfers between the I/O memories of two I/O devices that wish to exchange data. When the DMA controller is used in conjunction with bursting, transfers of data between I/O devices occur with minimal system bus usage. However, the DMA controller circuitry within the MPC860 chip has been observed to be relatively slow at performing dat
Cisco Technology Inc.
Hamilton Brook Smith & Reynolds PC
Namazi Mehdi
Yoo Do Hyun
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