Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1999-06-03
2001-10-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S525000, C438S592000, C438S744000, C438S745000
Reexamination Certificate
active
06309983
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to the formation of oxides in semiconductor fabrication.
2. Description of the Related Art
Semiconductor memory devices, such as dynamic random access memories (DRAM's) include capacitors accessed by transistors to store data. Deep trench (DT) capacitors are among the types of capacitors used in DRAM technology. Deep trench capacitors are typically buried within a semiconductor substrate.
Processing of semiconductor devices such as DRAM's requires formation and subsequent removal of sacrificial films such as SiO
2
which are called sacrificial oxides (SacOx). These SacOx films may have different uses, such as
1. surface protection, e.g., during implantation, or etch processes (e.g., prior to gate oxide formation);
2. stress relief film (e.g., Pad Oxide);
3. etch stop layer (e.g., Pad Oxide);
4. smoothing of the surface (e.g., SacOx in deep trenches);
5. masking layers (e.g. metal hard mask with subsequent oxidation);
6. structure formation (Poly Pillar formation within deep trenches, DT bottle shape formation); and
7. channeling inhibition during ion implantation.
The conventional thermal SacOx formation suffers from at least some the following drawbacks:
1. High temperatures, up to 1050 ?C., are required. This significantly contributes to the thermal process budget and may cause stress at device interfaces resulting in dislocations. These dislocations may e.g. cause variable retention time (VRT) problems.
2. The oxide thickness of high temperature SacOx. shows a severe dependence on the Si-crystal orientation resulting in nonuniform structures if polycrystalline surfaces such as trench sidewalls are involved.
3. Thermal SacOx thickness measurement and control are needed. Conventionally the SacOx thickness is measured on the surface of monitor wafers, i.e. an indirect measurement is performed which has to be correlated to the actual structure. If the surface has a different crystal orientation or is polycrystalline (e.g., trench sidewalls), this results in significant deviations between measurement and actual thickness (poor control).
4. Thermal oxides show a high density and are therefore relatively resistant to wet etches. The removal of thermal oxides therefore often results in an undesired attack (degradation) of exposed device surfaces.
5. To obtain homogeneous SacOx thicknesses across wafers, a high temperature uniformity is required resulting in the need for high quality furnaces which are expensive.
Therefore, a need exists for a method for forming a sacrificial oxide which does not suffer from the disadvantages of conventional processes. A further need exists for providing a sacrificial oxide process without significant impact to a thermal processing budget.
SUMMARY OF THE INVENTION
A method for depositing a sacrificial oxide for fabricating a semiconductor device includes the steps of preparing p-doped silicon regions on a semiconductor wafer for depositing a sacrificial oxide on the p-doped silicon regions, placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the p-doped silicon regions to form a sacrificial oxide on the p-doped silicon regions when a potential difference is provided between the wafer and the solution, and processing the wafer using the sacrificial oxide layer.
Another method, in accordance with the present invention, for electrochemically forming a sacrificial oxide includes the steps of exposing p-doped portions of a silicon substrate, placing the silicon substrate in an electrochemical cell, the electrochemical cell including a solution having electrolytes dissolved therein, applying a first potential to the silicon substrate and a second potential to the solution to form a potential difference therebetween such that a sacrificial oxide layer is electrochemically deposited on the exposed p-doped regions of the substrate, processing the wafer using the sacrificial oxide layer and removing the sacrificial oxide layer.
In alternate methods, the step of applying a voltage between the wafer and the solution to create the potential difference such that the voltage applied controls the thickness of the sacrificial oxide may be included. The solution preferably includes water and the electrolyte preferably includes an ionic compound. The step of placing the wafer in an electrochemical cell may include the steps of placing the wafer in an electrochemical cell such that the wafer has an exposed surface area including the exposed p-doped silicon regions thereon and providing a counter electrode in the solution having a substantially same exposed surface area as the exposed surface area of the wafer.
The step of placing the wafer in an electrochemical cell may include the step of sealing other than exposed areas of the wafer to prevent contact with the solution. The step of placing the wafer in an electrochemical cell may include the step of placing the wafer in an electrochemical cell such that a front surface of the wafer including the exposed p-doped silicon regions is exposed to an anodic or electrochemical oxidation and a back surface of the wafer is exposed to a second solution which transfers a potential to the wafer to cause the potential difference. The solution including electrolytes preferably interacts with the p-doped silicon regions by reacting according to the reaction:
Si+H
2
O→SiO
2
+4H
+
+4
e
−
(EQ. 1).
The reaction preferably occurs at about room temperature. The step of processing may include the steps of etching a trench in a substrate of the semiconductor wafer wherein the surface has a first smoothness, forming the sacrificial oxide layer in the trench, and etching the sacrificial oxide layer to form a surface smoother than the first smoothness. The step of processing may alternately include the steps of forming the sacrificial oxide layer on a surface of a substrate of the semiconductor wafer, and shielding portions of the surface from dopants using the sacrificial oxide layer. The step of processing may include the steps of etching a trench in a substrate of the semiconductor wafer, forming an oxide region in the trench, etching the oxide region to expand the trench. The step of adjusting a thickness of the sacrificial oxide by adjusting th e potential difference may also be included. The step of processing may include the steps of etching a trench in a substrate of the semiconductor wafer wherein the surface has a first smoothness and forming the sacrificial oxide layer in the trench. The step of removing may include the step of etching the sacrificial oxide layer to form a surface smoother than the first smoothness.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 5928968 (1999-07-01), Bothra et al.
patent: 6074900 (2000-06-01), Yamazaki et al.
Kudelka Stephan
Michaeli Alexander
Berry Renee′ R.
Infineon - Technologies AG
Nelms David
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