Semiconductor storage device

Details Semiconductor storage device Semiconductor storage device

2000-06-21

2001-10-16

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S205000, C365S207000

Reexamination Certificate

active

06304507

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device. In particular, the invention relates to a semiconductor storage device having a sense amplifier.
2. Description of Related Art
FIG. 4
is a circuit diagram showing a sense amplifier of a conventional semiconductor storage device. As shown in
FIG. 4
, the sense amplifier SA is connected to bit lines BL and /BL. The sense amplifier SA includes P-type MOS transistors PT
1
and PT
2
and N-type MOS transistors NT
1
and NT
2
. A series connection of the P-type MOS transistor PT
1
and the N-type MOS transistor NT
1
is provided between nodes SP and SN. A series connection of the P-type MOS transistor PT
2
and the N-type MOS transistor NT
2
is also provided between the nodes SP and SN. The gates of the P-type MOS transistor PT
1
and the N-type MOS transistor NT
1
are connected to the bit line /BL and a node N
2
that is located between the P-type MOS transistor PT
2
and the N-type MOS transistor NT
2
. The gates of the P-type MOS transistor PT
2
and the N-type MOS transistor NT
2
are connected to the bit line BL and a node N
1
that is located between the P-type MOS transistor PT
1
and the N-type MOS transistor NT
1
.
Next, the operation of this sense amplifier SA will be described below with reference to a timing chart of FIG.
5
.
FIG. 5
shows a case where the pre-charging potential is (Vdd+Vss)/2, that is, the middle potential between a power source potential Vdd and a ground potential Vss and information stored in the memory cell is read out and the potential of the bit line BL thereby becomes higher than that of the bit line /BL by &Dgr;V. In a state that information stored in the memory cell has been read out to cause a potential difference &Dgr;V between the bit lines BL and /BL, the potential of the node SN is decreased from (Vdd+Vss)/2 to the ground potential Vss. As a result, the N-type MOS transistors NT
1
and NT
2
are turned on. Since the potential of the bit line BL is higher than that of the bit line /BL, a current flowing through the N-type MOS transistor NT
2
is larger that a current flowing through the N-type MOS transistor NT
1
. Therefore, the potential of the bit line /BL decreases toward the ground potential Vss and the current flowing through the N-type MOS transistor NT
1
decreases. Therefore, the potential of the bit line BL decreases slightly and the potential difference between the bit lines BL and /BL increases.
Then, the potential of the node SP is increased from (Vdd+Vss)/2 to the power source potential Vdd. As a result, since the potential of the bit line /BL is lower than that of the bit line BL, a larger current flows through the P-type MOS transistor PT
1
than the P-type MOS transistor PT
2
. Therefore, the potential of the bit line BL increases toward the power source potential Vdd. As the potential of the bit line BL increases, the current flowing through the P-type MOS transistor PT
2
decreases. As a result, the potential difference between the bit lines BL and /BL is amplified to Vdd−Vss.
For a differential sense amplifier shown in
FIG. 4
to perform a normal amplifying operation, the potential difference &Dgr;V that occurs when information is read out from the memory cell should be larger than a certain value. Unless the memory cell capacitor has a large capacitance value, the potential difference &Dgr;V does not become larger than the certain value. Therefore, the size of the memory call cannot be reduced unduly. This is one factor of preventing reduction of the chip area.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor storage device which allows a differential sense amplifier to perform a normal amplifying operation even if a potential difference occurring in a pair of bit lines in readout of memory cell information is small.
According to an aspect of the present invention, there is provided a semiconductor storage device comprising: an inverting amplification circuit which includes: a first inverting amplifier having an input and an output that are connected to a first node and a second node, respectively, for inverting-amplifying a potential at the first node and supplying an amplified potential to the second node; and a second inverting amplifier having an input and an output that are connected to the second node and the first node, respectively, for inverting-amplifying a potential at the second node and supplying an amplified potential to the first node; and a differential amplification circuit connected to the first node and second node, for amplifying a difference between the potentials at the first node and the second node as amplified by the inverting amplification circuit.
The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiments thereof taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5220527 (1993-06-01), Ohsawa
patent: 5323345 (1994-06-01), Ohsawa
patent: 6009032 (1999-12-01), Lin et al.
patent: 6104655 (2000-08-01), Tanoi et al.
patent: 9-251782 (1997-09-01), None

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