Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-05-19
2001-10-02
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S672000, C438S675000, C438S688000
Reexamination Certificate
active
06297156
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and in particular, the present invention relates to an alloy for enhanced filling of dual damascene structures.
BACKGROUND OF THE INVENTION
As the density of semiconductor devices continues to increase, the need for smaller interconnections also increases. Historically, the semiconductor industry has used a subtractive etching process to pattern metal interconnect layers of the semiconductor. This metal processing technique, however, has limitations including poor step coverage, non-planarity, shorts and other fabrication problems. To address these problems, a dual damascene technique has been developed. This process, as explained in “Dual Damascene: A ULSI Wiring Technology”, Kaanta et al., 1991 VMIC Conference, 144-150 (Jun. 11-12, 1991) and incorporated hereinto reference, involves the deposition of a metal into contact vias and conductor trenches which are patterned in the semiconductor. The semiconductor is then subjected to a known CMP (chemical-mechanical polish) process to both planarize the semiconductor and to remove excess metal from all but the patterned areas.
The metal layer can be fabricated using known CVD (chemical vapor deposition) or PVD (physical vapor deposition) techniques. Filling the patterned structures formed during the dual damascene technique, however, has proved difficult. This difficulty is enhanced as the aspect ratio (depth to width) of the patterns increase. As such, the use of high pressure to achieve improved fill in sub-micron conductor processing for ULSI integrated circuits has received considerable attention recently. One of the problems encountered is that high temperatures must be combined with high pressure to achieve conditions where sufficient metal flow will take place to fill the narrow troughs in the damascene process.
During the metal deposition process, an aluminum alloy which may contain such elements as copper and silicon, is deposited on the integrated circuit wafer. Aluminum has been typically used due to its low resistance and good adhesion to SiO
2
and Si. Silicon is usually added as an alloying element to alleviate junction spiking in Al contacts to Si. Further, electromigration and hillocks (spike-like formations) can be reduced by adding Cu, Ti, Pd or Si to aluminum to form alloys. These alloying elements precipitate at the grain boundaries. Thus, the grain boundaries are “plugged” and vacancy migration is inhibited.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an alloy which can be used to fill high aspect ration structures in an integrated circuit without requiring high temperatures or pressures. Specifically, an alloy and alloy system is needed which will enable force fill to be achieved at lower temperatures and/or lower pressures than can be obtained with the standard Al-0.5% Cu alloy which is used by much of the industry.
SUMMARY OF THE INVENTION
The above-mentioned problems with metal interconnect alloys in an integrated circuit and other problems are addressed by the present invention, and which will be understood by reading and studying the following specification. A method of forming an interconnect alloy is described which reduces temperature and pressure needed to fabricate high aspect ratio features.
In particular, a method of fabricating an integrated circuit is described. The method comprises the steps of forming contact vias and interconnect trenches in a dielectric layer of the integrated circuit, depositing a metal alloy in the contact vias and interconnect trenches, and polishing the integrated circuit to remove excess metal alloy and provide defined interconnect lines. The alloy comprises aluminum, 4.5 to 5.5 wt percent copper and 1 to 1.5 wt percent silicon.
In one embodiment a method of fabricating high aspect ratio features in an integrated circuit is provided which comprises forming contact vias and interconnect trenches in a dielectric layer of the integrated circuit, depositing a metal alloy in the contact vias and interconnect trenches at force fill temperatures of 300° centigrade, the metal alloy having a resistivity of approximately sixteen percent higher than high purity aluminum, and polishing the integrated circuit to remove excess metal alloy and provide defined interconnect lines.
In another embodiment, a method of fabricating high aspect ratio features in an integrated circuit is provided which comprises forming contact vias and interconnect trenches in a dielectric layer of the integrated circuit, depositing a metal alloy in the contact vias and interconnect trenches at force fill temperatures of 300 centigrade, the alloy having a resistivity of approximately eight percent higher than 0.5 percent copper alloy processed at 400° C., and polishing the integrated circuit to remove excess metal alloy and provide defined interconnect lines.
In another embodiment, a method of fabricating high aspect ratio features in an integrated circuit is provided which comprises forming contact vias and interconnect trenches in a dielectric layer of the integrated circuit, depositing a metal alloy in the contact vias and interconnect trenches at force fill temperatures of 300° centigrade, the alloy comprising an alloying material that does not form volatile fluorides during an etch process, and polishing the integrated circuit to remove excess metal alloy and provide defined interconnect lines.
In yet another embodiment, a method of fabricating high aspect ratio features in an integrated circuit is provided which comprises forming contact vias and interconnect trenches in a dielectric layer of the integrated circuit, depositing a metal alloy in the contact vias and interconnect trenches, the alloy comprising aluminum, 3 to 6 wt percent copper, and 0.25 to 1.5 wt percent silicon, and polishing the integrated circuit to remove excess metal alloy and provide defined interconnect lines.
REFERENCES:
patent: 3561954 (1971-02-01), Brook
patent: 4393096 (1983-07-01), Gajda
patent: 4595429 (1986-06-01), Le Caer et al.
patent: 5071791 (1991-12-01), Inoue et al.
patent: 5205770 (1993-04-01), Lowrey et al.
patent: 5229316 (1993-07-01), Lee et al.
patent: 5300155 (1994-04-01), Sandhu et al.
patent: 5354712 (1994-10-01), Ho et al.
patent: 5395801 (1995-03-01), Doan et al.
patent: 5409563 (1995-04-01), Cathey
patent: 5416045 (1995-05-01), Kauffman et al.
patent: 5497017 (1996-03-01), Gonzales
patent: 5527561 (1996-06-01), Dobson
patent: 5641545 (1997-06-01), Sandhu
patent: 5644166 (1997-07-01), Honeycutt et al.
patent: 5994221 (1999-11-01), Kizilyalli et al.
patent: 6017144 (2000-01-01), Guo et al.
patent: 6090710 (2000-07-01), Andricacos et al.
patent: 6110829 (2000-08-01), Besser et al.
patent: 1211563 (1970-11-01), None
patent: 61159545A (1986-07-01), None
patent: 63179041A (1988-07-01), None
patent: 60107654A (1995-09-01), None
Kaanta, C., et al., “Dual Damascene: A ULSI Wiring Technology”,VMIC Conference, 144-152, (Jun. 1991).
Licata, T., et al., “Dual Damascene AL Wiring for 256M DRAM”,VMIC Conference, 596-602, (Jun. 1995).
Zolotorevski, V.S., et al., “Effect of magnesium + Germanium and Magnesium + Silicon Additives on MechanicalProperties and Structure of Cast Aluminum-Copper Alloys”, Izy,Vysah, Uchebn, Zaved, Tsvern, Metall., 5, 100-4,100-4, (1983).
Farrar Paul A.
Givens John H.
Malsawma Lex H.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
Smith Matthew
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