Semiconductor device with ESD protective circuit

Details Semiconductor device with ESD protective circuit Semiconductor device with ESD protective circuit

1999-06-29

2001-12-11

Williams, Alexander O. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S173000, C257S355000, C257S356000, C257S357000, C257S360000, C257S546000, C257S362000, C257S174000

Reexamination Certificate

active

06329694

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device with an electrostatic discharge (ESD) protective circuit formed therein. Particularly, the present invention relates to an ESD protective circuit in which an n-well guard ring or an n
+
guard ring is formed around an NMOS field transistor of a data input buffer or around an NMOS transistor of a data output buffer, so as to strap the n-well guard ring or the n
+
guard ring to an n-well of a PMOS field transistor and to an n-well of a PMOS transistor, so that the electrical resistance between the wells of the NMOS transistor and the PMOS transistor can be reduced, thereby improving the characteristics of the ESD protective circuit and a latch-up device, and improving the characteristics and the reliability of the semiconductor device.
2. Description of the Prior Art
Generally, if a semiconductor device is exposed to an electrostatic discharge, its internal circuit is damaged, with the result that the semiconductor device shows malfunctions and causes a reliability problem.
Such a damage of the internal circuit is caused by the following mechanism. That is, if an electrostatic discharge occurs, the electric charges which have been injected through an input terminal move through the internal circuit to another terminal. Under this condition, due to the joule heat, junction spiking, oxide layer ruptures and the like occur.
In order to solve this problem, the charges which have been injected during the electrostatic discharge have to be dissipated toward the power supply terminal before the charges pass through the internal circuit. For this purpose, an ESD protective circuit has to be provided.
As shown in
FIG. 1
, an ESD protective circuit of an input pin consists of NMOS and PMOS transistors, this being one case. In
FIG. 2
, a data output driver consists of NMOS and PMOS transistors, this being another case. In all of these two cases, a gate diode is formed between a power voltage VCC and a ground voltage Vss. Thus if Vss is in a positive mode, the current of the NMOS transistor (which serves as a main bipolar transistor) is dispersed, and thus, the current is made to pass from a PMOS p
+
diffusion layer through an n-well to a PNPN path which is connected to a bipolar between Vcc and Vss. In this manner, the strength of the ESD protective circuit is reinforced.
However, in the semiconductor device with the above-described conventional ESD protective circuit, the current cannot sufficiently flow to the PNPN path due to the resistance of the Vcc power line. Further, an additional layout area is required owing to the provision of the gate diode between Vcc and Vss.
SUMMARY OF THE INVENTION
The present invention is intended to overcome the above-described disadvantages of the conventional techniques.
Therefore it is an object of the present invention to provide a semiconductor device with an ESD protective circuit, in which an n-well guard ring or an n
+
guard ring is formed around an NMOS field transistor of a data input buffer or around an NMOS transistor of a data output buffer, so as to connect the n-well guard ring or the n
+
guard ring to an n-well of a PMOS field transistor and to an n-well of a PMOS transistor and so as to carry out a strapping, so that the electrical resistance between the wells of the NMOS transistors and the PMOS transistors can be reduced, thereby improving the characteristics and the reliability of the semiconductor device.
In achieving the above object, the semiconductor device with an ESD protective circuit using a PMOS transistor and an NMOS transistor as the ESD protective circuit of a data output driver according to the present invention, includes: an n-well guard ring formed around the NMOS transistor, the n-well guard ring being strapped to an n-well of the PMOS transistor.
In another aspect of the present invention, the semiconductor device with an ESD protective circuit using a PMOS field transistor and an NMOS field transistor as an input ESD protective circuit according to the present invention, includes: an n-well guard ring formed around the NMOS field transistor, the n-well guard ring being strapped to an n-well of the PMOS field transistor.
In still another aspect of the present invention, the semiconductor device with an ESD protective circuit using a PMOS field transistor and an NMOS field transistor as an input ESD protective circuit according to the present invention, includes: a p
+
guard ring formed around the PMOS field transistor, the p
+
guard ring being strapped to an p
+
pick-up of the NMOS field transistor.


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