Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-03-23
2001-12-25
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S640000, C438S701000
Reexamination Certificate
active
06333258
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, it relates to a method of manufacturing a semiconductor device having a multilayer wiring structure as is employed for the device processes of 0.25 [&mgr;m] generation et seq.
2. Description of the Related Art
With the microfabrication of semiconductor devices, it has been necessitated to fine wiring lines and reduce a wiring pitch within the semiconductor device. It has also been necessitated to lower the permittivity of an inter-layer insulating film and lower the resistances of the wiring lines, as a lower power dissipation, a higher operating speed etc. have been required of the semiconductor device. In order to achieve the necessities, it has become necessary that copper is used for a wiring material, while a low-permittivity insulating material affording a permittivity of 3.0 or below, such as an organic material including fluorocarbon resin, or as xerogel, is used for a material which is inlaid between wiring layers and the wiring lines.
On the other hand, at the present time at which etching technology for copper has not been established yet, the adoption of a damascene process is indispensable for the application of the metal copper to the wiring material. However, when the steps of a single damascene process for individually forming the wiring line and a plug are merely combined, the number of the steps enlarges to increase both a production cost and a lead time, and this is very disadvantageous in the production of the semiconductor device.
It is therefore desired to establish a dual damascene process in which a wiring groove and a contact hole are simultaneously formed in an insulating material, and in which the wiring line and the plug for one layer are simultaneously formed by the inlaying of an electric conductor such as metal and chemical mechanical polishing (hereinbelow, abbreviated to “CMP”). It is especially wished for to establish a dual damascene process in which a low-permittivity material capable of diminishing wiring capacitances is used as the insulating material between wiring lines and wiring layers.
An etching technique for the low-permittivity material is important for realizing the dual damascene process which uses the low-permittivity material. In particular, the low-permittivity material of organic type has etching characteristics similar to those of a resist mask. It is therefore difficult to employ a resist for a mask for the low-permittivity material. Accordingly, a pattern made of the resist is transferred onto an inorganic material film, thereby to prepare a so-called “hard mask”, and the low-permittivity material is etched using the hard mask as the etching mask. In addition, at the present time at which CMP technology for the low-permittivity material has not been satisfactorily developed yet, the hard mask plays also the role of a margin for cutting at the step of the CMP. Therefore, a silicon oxide film is mainly employed as the hard mask material.
In case of forming a dual damascene structure, a manufacturing method to be explained below has heretofore been proposed.
As shown in
FIG. 1A
of the accompanying drawings, a substrate
110
which is formed with a semiconductor element (not shown), a first wiring line
111
, a barrier layer
112
, etc. is overlaid with a connection layer
113
which serves as an inter-layer insulating film part to be formed with a contact hole. Thereafter, a hard mask (intermediate layer)
115
provided with a contact hole pattern
114
is formed, and it is overlaid with a wiring layer
116
which serves as an inter-layer insulating film part to be formed with a second wiring line. Further, a hard mask
117
to be provided with a wiring groove pattern is formed.
Subsequently, the hard mask
117
is etched using a resist mask
119
formed with a wiring groove pattern
118
. Besides, as shown in
FIG. 1B
, the hard mask
117
is formed with an opening
120
(wiring groove pattern) for forming a wiring groove. Next, the wiring layer
116
is etched using the hard mask
117
as an etching mask, thereby to form a wiring groove
121
. The etching is further caused to proceed until a contact hole
122
is formed in the connection layer
113
as shown in
FIG. 1C
, by employing the hard mask
115
as an etching mask.
At the next step, as shown in
FIG. 1D
, that part of the barrier layer
112
which lies at the bottom of the contact hole
122
is etched to denude the first wiring
111
. Thereafter, a barrier layer
123
is formed on the walls of the wiring groove
121
and the contact hole
122
by a known copper inlaying technique. Further, the second wiring line
124
and a plug
125
are respectively formed in the wiring groove
121
and the contact hole
122
by a copper film forming technique such as copper plating. Then, a wiring structure is finished up.
With the above manufacturing method, however, the intermediate layer requires a thickness of at least 50 [nm] for the reason that it needs to function as the etching mask in forming the contact hole by the etching. It is therefore difficult to make the intermediate layer thinner than 50 [nm]. Moreover, in the case of using the organic material for the inter-layer insulating film, an inorganic film needs to be used as the intermediate layer. The inorganic film exhibits a comparatively high permittivity on account of the property of an inorganic material. By way of example, a silicon oxide film has a permittivity of 4.2 or so. The prior-art method is therefore difficult of lowering the effective permittivity of the whole wiring structure by thinning the intermediate layer.
SUMMARY OF THE INVENTION:
The present invention has for its object to provide a method of manufacturing a semiconductor device as solves the problems stated above.
Concretely, the present invention resides in a method of manufacturing a semiconductor device which has an inter-layer insulating film, characterized by comprising the step of forming an inorganic film on the inter-layer insulating film, the inorganic film being to serve as an etching mask in a case where said inter-layer insulating film is etched; the step of forming a first opening pattern in an upper part of the inorganic film, the first opening pattern serving to form a wiring groove in the inter-layer insulating film; and the step of forming a second opening pattern in the inorganic film, the second opening pattern serving to form a contact hole in the inter-layer insulating film and being formed so as to coincide with the first opening pattern at least partially.
The method of manufacturing a semiconductor device further comprises the step of forming the contact hole in the inter-layer insulating film by employing as the etching mask the inorganic film formed with the first opening pattern and the second opening pattern; the step of etching the inorganic film into a state where it is formed with only a third opening pattern obtained by transferring the first opening pattern; and the step of forming the wiring groove in the inter-layer insulating film by employing as an etching mask the inorganic film formed with the third opening pattern.
With the above method of manufacturing a semiconductor device, the inorganic film is formed on the inter-layer insulating film, the first opening pattern for forming the wiring groove is formed in the upper part of the inorganic film, and the second opening pattern for forming the contact hole is formed in the inorganic film, so that the etching mask is formed of the single-layer inorganic film. Therefore, the intermediate layer as in the prior art, which functions as the etching mask in the case of forming the contact hole, need not be provided, so that the step of forming the intermediate layer can be omitted.
Furthermore, when the depth of the wiring groove is determined by controlling the etching time period for forming the wiring groove, the intermediate layer is not necessary at all. As compared with
Hasegawa Toshiaki
Miyata Koji
Taguchi Mitsuru
Everhart Caridad
Kananen Ronald P.
Rader & Fishman & Grauer, PLLC
Sony Corporation
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