Method of forming T-shaped gate

Details Method of forming T-shaped gate Method of forming T-shaped gate

2000-02-24

2001-05-29

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S182000

Reexamination Certificate

active

06239007

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 088121711, filed Dec. 10, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming the gate of an integrated circuit device. More particularly, the present invention relates to a method of forming a T-shaped gate.
2. Description of the Related Art
As the level of integration of integrated circuit rises, dimensions of each semiconductor device are reduced and the adverse effects of having a narrow line width are more prominent.
To counteract the rapid increase in sheet resistance due to a narrow line width, a metal silicide layer is formed over the source, drain and gate terminals of a transistor. Hence, electrical conductivity between a transistor terminal and a conductive line is increased.
Conventionally, the metal silicide layer over transistor terminals is formed by a self-aligned silicide (Salicide) process. After a transistor consisting of a polysilicon gate, a gate oxide layer, a source terminal, a drain terminal and spacers is formed, a metallic layer is formed over the transistor. A thermal operation is conducted so that metallic atoms in the metallic layer can react with silicon atoms on the surface of the polysilicon gate, the source terminal and the drain terminal to form a metal silicide layer. finally, the unreacted metal is removed.
Another method of lowering sheet resistance at the gate besides forming a silicide layer over the gate is to form a T-shaped gate terminal. However, a selective silicon growth process is the conventional method of forming a T-shaped gate terminal. Selective silicon growth is an expensive process and has a small processing window. Therefore, cost of production is high and throughput is low, which means it is not suitable for volume production in a manufacturing facility.
SUMMARY OF THE INVENTION
The invention provides a method of forming a T-shaped gate. A semiconductor substrate is provided. A gate structure is formed over the semiconductor substrate. A first insulation layer is formed over the gate structure and the semiconductor substrate, and then a second insulation layer is formed over the first insulation layer. The second insulation layer is planarized so that a portion of the first insulation layer above the gate structure is exposed. The first insulation layer above the gate structure is removed to expose the top surface of the gate structure. A conductive layer is next formed over the gate structure and the second insulation layer. The conductive layer above the second insulation layer is removed retaining the conductive layer above the gate structure. Finally, the first insulation layer and the second insulation layer are removed while using the conductive layer above the gate structure as an etching mask.
In the present invention, two insulation layers, each having a different etching rate, are sequentially formed over a conventional gate structure. A planarization of one of the insulation layers is next carried out. Utilizing the difference in etching rate between the two insulation layers, the insulation layer above the gate structure is removed to expose the gate structure. A conductive layer is then formed over the exposed gate structure. Another planarization is carried out so that only the portion of conductive layer above the gate structure is retained. While using the conductive layer above the gate structure as an etching mask, the two insulation layers are removed. Finally, a silicide process is carried out to form a silicide layer over the conductive layer.
Sheet resistance of the T-shaped gate terminal is lowered in the invention without a corresponding increase in gate dimensions. Hence, the narrow line effect due to dimensional reduction is improved.
In the process of forming the T-shaped gate terminal, processes having a larger processing window and less expensive operating cost than conventional selective silicon growth process are used. Hence, productive cost is reduced and throughput is increased, which means the process of the invention is more suitable for large-scale production.
Accordingly, the present invention provides a method of forming a T-shaped gate having a higher processing window and a lower cost of production than the conventional selective silicon growth process.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4839304 (1989-06-01), Morikawa
patent: 4849376 (1989-07-01), Balzan et al.
patent: 6159781 (2000-12-01), Pan et al.

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