Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-01-31
2001-07-03
Bowers, Charles (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S149000
Reexamination Certificate
active
06255147
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to silicon on insulator (SOI) circuit structure fabrication techniques, and more specifically to an SOI field effect transistor (FET) fabrication technique.
BACKGROUND OF THE INVENTION
Conventional or bulk semiconductor transistors are formed in a semiconductor substrate by implanting a well of either P-type or N-type conductivity silicon in a silicon substrate wafer of the opposite conductivity. A field oxide layer functions to prevent surface inversion. Gates and source/drain diffusions are then manufactured using commonly known processes. These form devices known as metal-oxide-semiconductor (MOS) field effect transistors (FETs). Each of these FETs must be electrically isolated from the others in order to avoid shorting the circuits. These FET's are typically interconnected through metal layers above the bulk substrate to form logic circuits. Typically, the interconnections will be structured to interconnect both P-Channel and N-Channel FET's in accordance with known complimentary metal oxide semiconductor (CMOS) techniques to minimize power consumption.
A problem with bulk semiconductor logic circuits is that a relatively large amount of surface area is needed for the electrical isolation of the various FETs which is undesirable for the current industry goals for size reduction. Additionally, junction capacitance between the source/drain and the bulk substrate slows the speed at which a device using such transistors can operate.
In order to deal with the junction capacitance problem and reduce size, silicon on insulator technology (SOI) has been gaining popularity. One method of forming an SOI wafer includes using conventional oxygen implantation techniques to create an insulating buried oxide layer at a predetermined depth below the surface of a bulk wafer. The implanted oxygen oxidizes the silicon into insulating silicon dioxide in a guassian distribution pattern centered at the predetermined depth to form the insulating buried oxide layer. A second method of forming an SOI wafer includes depositing an insulating layer of silicon dioxide on the surface of a first wafer and then bonding such wafer to a second wafer using a heat fusion process.
Utilizing SOI technology, an SOI FET includes a source region and drain region of a first semiconductor type on opposing sides of a channel region of the opposite semiconductor type. An SOI FET is isolated by etching a trench around the periphery of an island in the thin semiconductor layer above the insulating buried oxide layer in the SOI wafer. Appropriate portions of the island are then doped to form the source region, drain region, and channel region. It is recognized in the art that an SOI FET will occupy less surface area on the substrate and, because it is isolated from the silicon substrate by the insulating trench and the insulating buried oxide layer, will have a lower junction capacitance than an equivalent bulk semiconductor FET. This provides for the ability to put larger logic circuits in less space and operate such circuits with reduced power consumption.
However, the power consumption at which an SOI FET can operate is still limited by the dimension between the channel/source junction and the channel/drain junction. While it is recognized that a narrower channel region will provide for reduced power consumption, known SOI fabrication techniques have a limited resolution resulting in a minimum island size.
Accordingly, there is a strong need in the art for an SOI circuit structure, and a method for forming such structure, that includes an SOI FET structure that provides for reduced channel width and reduced FET capacitance to provide for reduced power consumption operation.
SUMMARY OF THE INVENTION
A first aspect of this invention is to provide a method of forming a narrow circuit component on a silicon on insulator wafer, comprising: a) forming a photoresist mask with a length dimension and a width dimension over a silicon device layer to mask a device island region and expose a peripheral trench region; b) trimming a trim region of the photoresist mask to decrease at least one of the length dimension and the width dimension; and c) etching the peripheral trench region of the silicon device layer to isolate the island region. The method may further include forming a silicon nitride layer between the mask and the silicon device layer and the step of etching further includes etching the silicon nitride layer, any buffer oxide and the trench itself in the underlying silicon.
The step of trimming may include eroding the trim region using a chemical selective between the photoresist mask and silicon nitride, such as oxygen/fluorine.
The method of forming a narrow circuit component on a silicon on insulator wafer may further include filling the peripheral trench region with insulating silicon dioxide and may further yet include forming a silicon on insulator field effect transistor in the island region.
A second aspect of this invention is to provide method of forming a narrow circuit component on a silicon on insulator wafer, comprising: a) forming a mask over a silicon device layer to mask a device island region and expose a peripheral trench region with a width dimension; b) trimming a trim region of the photoresist mask to increase the width dimension of the peripheral trench region; and c) etching the peripheral trench region of the silicon device layer to isolate the island region. The method may further include forming a silicon nitride layer between the mask and the silicon device layer and the step of etching further includes etching the silicon nitride layer.
The step of trimming may include eroding the trim region using a chemical selective between the mask and silicon nitride, such as oxygen/fluorine.
The method of forming a narrow circuit component on a silicon on insulator wafer may further include filling the peripheral trench region with insulating silicon dioxide and may further yet include forming a silicon on insulator field effect transistor in the island region.
REFERENCES:
patent: 3997367 (1976-12-01), Yau
patent: 5055383 (1991-10-01), Koblinger et al.
patent: 5561076 (1996-10-01), Yoshino
patent: 5804856 (1998-09-01), Ju
patent: 5811855 (1998-09-01), Tyson et al.
patent: 5825696 (1998-10-01), Hidaka et al.
patent: 5846857 (1998-12-01), Ju
patent: 5877046 (1999-03-01), Yu et al.
patent: 5879975 (1999-03-01), Karlsson et al.
patent: 5894152 (1999-04-01), Jaso et al.
patent: 6107172 (2000-08-01), Yang et al.
patent: 6197644 (2001-03-01), Gardner et al.
patent: 6197687 (2001-03-01), Buynoski
Advanced Micro Devices , Inc.
Bowers Charles
Pert Evan
Renner Otto Boisselle & Sklar
LandOfFree
Silicon on insulator circuit structure with extra narrow... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Silicon on insulator circuit structure with extra narrow..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon on insulator circuit structure with extra narrow... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2567359