Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-08-30
2001-10-09
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S030000, C326S121000
Reexamination Certificate
active
06300799
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a signal line driver for the transmission and output of a binary signal such as a digital signal.
BACKGROUND OF INVENTION
For this type of a signal line driver, a bus driver, a line driver, etc. can be used.
FIG. 6
shows a circuit diagram for a conventional address driver that is used in an address buffer or the like within a semiconductor memory device.
FIG. 7
shows the signal waveform of each section of this address driver.
This address driver is designed with a one bit address signal input (AIN), and a pair of complementary address signal outputs (AOUT, AOUT_) having either an H level or an L level in response to the logic value of this input address signal (AIN).
This address driver is constructed of input stage inverters
100
,
102
,
104
that regulate the voltage level of the input address signal (AIN) to the logic level of a reference voltage, NAND gates
106
,
108
that regulate the pulse period of the output address signals (AOUT, AOUT_), and the output stage inverters
110
,
112
that electrically drive the pair of bus lines (AL, AL_), respectively, in order to transmit the output address signals (AOUT, AOUT_). The other end (receive end) of the bus lines (AL, AL_) are connected at the receiver side, for example, to the input terminal of an input buffer for an address decoder or a receiver (not illustrated).
In the interval that the address signals (AOUT, AOUT_) are not output, the address enable signal (AEN) is in an inactive state (L level), the outputs of both NAND gates
106
,
108
are each held at an H level, and the outputs of both inverters
110
,
112
and the bus lines (AL, AL) are all held at an L level that is equal to the power supply voltage (V
SS
) (for example, 0 volts).
At the same time an address signal (AIN) is input, an address enable signal (AEN) is activated for a prescribed period, for example, for the pulse period, and during this pulse period, both NAND gates
106
,
108
are turned on.
When the logic level of the address signal (AIN) is “1” (H level), the output of the NAND gate
106
becomes an L level, and due to this, the output of the inverter
110
becomes an H level that is nearly equal to the power supply voltage (V
DD
) (for example, 3.3 volts). On the other hand, the output of the NAND gate
108
remains at the H level, and the output of the inverter
112
remains at the L level that is equal to (V
SS
). By this means, during the pulse period that is regulated by means of the address enable signal (AEN), an address signal (AOUT) having an H level that is nearly equal to (V
DD
) is output on the bus line (AL); and a complementary address signal AOUT_) having an L level that is nearly equal to (V
SS
) is output on the bus line AL_.
Conversely, when the logic value of the address signal (AIN) is “0” (L level), during the pulse period, an address signal (AOUT) having an L level that is nearly equal to (V
SS
) is output on one of the bus lines (AL), and a complementary address signal (AOUT_) having an H level that is nearly equal to (V
DD
) is output on the other bus line (AL_).
Problems to be solved by the invention
As was mentioned above, a conventional signal line driver of this type can transmit and output a binary signal having an H level that is nearly equal to (V
DD
) and an L level that is nearly equal to (V
SS
) due to the fact that the output stage inverters
110
,
112
drive the signal lines (bus lines) AL, AL_at the full amplitude of both power supply voltages (V
DD
, V
SS
).
However, in a DRAM (dynamic RAM), for example, as the storage capacity increases, the chip surface area also increases and the signal lines within the chip become longer, and the transmission delay time on the bus becomes impossible to ignore. Also, in a high-speed memory such as a synchronous DRAM, the transfer cycle for the signal is fast, and because as a general rule the address width (number of address bits) is also large, the electrical power that is consumed by the bus driver also becomes impossible to ignore.
The present invention was designed with consideration of these types of problems, and its purpose is to disclose a signal line driver that reduces the power consumption and shortens the transmission delay time.
SUMMARY OF THE INVENTION
In order to achieve the above-mentioned purposes, a first aspect of the present invention is a signal line driver that electrically drives a signal line for the purpose of transmitting a binary signal that has a bias means that holds the above-mentioned signal line at a first voltage level in the interval the above-mentioned binary signal is not being transmitted, a switching means that is connected between the above-mentioned signal line and a power supply voltage terminal that supplies a second voltage level, and a switch control means that holds the above-mentioned switching means in the OFF condition in the interval the above-mentioned binary signal is not being transmitted, conditionally switches the above-mentioned switching means to the ON condition in response to the logic value of the above-mentioned binary signal when the above-mentioned binary signal is being transmitted, and returns the above-mentioned switching means to the OFF condition when the voltage of the above-mentioned signal line reaches a prescribed voltage level.
Another aspect of the present invention is a signal line driver that electrically drives a first and second signal line complementarily in order to transmit one binary signal that has a first and second bias means that hold the above-mentioned first and second signal line respectively at a first voltage level in the interval the above-mentioned binary signal is not being transmitted, a first and second switching means that connects between the above-mentioned first and second signal lines respectively and a power supply voltage terminal that supplies a second voltage level, and a switch control means that holds the above-mentioned first and second switching means in the OFF condition in the interval the above-mentioned binary signal is not being transmitted, switches one of the above-mentioned first or second switching means to the ON condition in response to the logic value of the above-mentioned binary signal when the above-mentioned binary signal is being transmitted and holds the other in the OFF condition, and returns the above-mentioned switching means to the OFF condition when the voltage of the above-mentioned signal line that is connected to the above-mentioned switching means reaches a prescribed voltage level.
A third aspect of the invention is a signal line driver that electrically drives a signal line for the purpose of transmitting a binary signal in a pulse waveform that has a bias means that maintains the above-mentioned signal line at a first voltage level in the interval the above-mentioned binary signal is not being transmitted, a switching means that is connected between the above-mentioned signal line and a power supply voltage terminal that supplies a second voltage level, and a switch control means that holds the above-mentioned switching means in the OFF condition in the interval the above-mentioned binary signal is not being transmitted, conditionally switches the above-mentioned switching means to the ON condition in response to the logic value of the above-mentioned binary signal when the above-mentioned binary signal is being transmitted, and returns the above-mentioned switching means to the OFF condition when a prescribed period that is shorter than the pulse period has elapsed.
A fourth aspect of the invention is a signal line driver that electrically drives a first and second signal line complementarily for the purpose of transmitting a binary signal of a pulse waveform that has a first and second switching means that holds the above-mentioned first and second signal lines respectively at a first voltage level in the interval the above-mentioned binary signal is not being transmitted, a first and second switching means that are connected between the above-mentioned first and second sign
Kempler William B.
Tan Vibol
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tokar Michael
LandOfFree
Signal line driver having reduced transmission delay time... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Signal line driver having reduced transmission delay time..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal line driver having reduced transmission delay time... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2566791