Electrical computers and digital processing systems: processing – Processing control – Mode switch or change
Reexamination Certificate
1998-09-30
2001-10-23
Lee, Thomas (Department: 2182)
Electrical computers and digital processing systems: processing
Processing control
Mode switch or change
C712S214000, C712S225000
Reexamination Certificate
active
06308262
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to the field of computer systems, and in particular, to an apparatus and method for performing efficient processing of instructions.
2. Description of the Related Art
Efficient processing of instructions in processors results in increased system performance. However, the processing of instructions is not always optimized. For example, address computation in processors that conform to the Intel Architecture (IA) 32 format typically requires the addition of three values, namely, the segment base address, the base address of the address within the segment [hereinafter “base address”] and an offset. A 3-input adder(s) is typically used to provide such address computation. In some of the more aggressive processor designs, the performance of a 3-input add may require 2 processor clock cycles, while a 2-input add may be performed within a single processor clock cycle.
Increased address computation latency results in performance degradation, particularly in applications which exhibit a large number of address generation interlocks. Accordingly, there is a need in the technology for providing an apparatus and method for performing efficient processing of instructions, such as address computation, so as to avoid the aforementioned problems.
BRIEF SUMMARY OF THE INVENTION
An apparatus and method for performing efficient processing of instructions is described. In one embodiment, a processor comprises a storage area to store a data operand and a control unit that is coupled to the storage area. A first circuit is coupled to the storage area and the control unit, which performs a first operation under a first condition. A second circuit is coupled to the storage area and the control unit, which performs a second operation under a second condition. The control unit operates on data elements in the data operand to process an instruction, and determines if processing of the instruction is to be performed under the second condition. If so, the second circuit is selected to process the instruction, otherwise the first circuit is selected to process the instruction. Various embodiments are disclosed.
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Blakely , Sokoloff, Taylor & Zafman LLP
Cao Chun
Intel Corporation
Lee Thomas
LandOfFree
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