Pulse width modulation method of inverter

Electrical transmission or interconnection systems – Plural load circuit systems – Control of current or power

Reexamination Certificate

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Reexamination Certificate

active

06333569

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to pulse width modulation methods of three-level inverters, and more particularly, to a pulse width modulation method of a three-level inverter, thereby enabling reduction of electric loss of the inverter.
DESCRIPTION OF THE RELATED ART
Typically, a three-level inverter has a pair of condensers connected in series with each other, having a neutral point, and a plurality of switches connected to their respective coils for switching on and off the coils. The three-level inverter has been used in comparatively high-capacity systems. In the three-level converter, the term “level” means a state of voltage; and thus, “three-level” means “three states of voltages.”
A three-level inverter has a plurality of a pair of voltage vectors, the pairs of voltage vectors indicating the same output voltages. While the pairs of voltage vectors indicate the same output voltages, they influence reversely upon change of voltages at direct current (DC) terminals. One voltage vector of the pair of voltage vectors raises the voltage of a condenser whereas the other voltage vector drops the voltage of that condenser reversely. Thus, if the voltage vector pairs are appropriately used, the same output voltages can be obtained, thereby maintaining a balance of voltages of the DC terminals.
For example, referring to
FIG. 2
which is a view showing output vectors of a three-level inverter according to the present invention, applicable output vectors where a command vector is located at Sector 1 have two sequences as in (0,0,0) →(1,0,0)→(1,1,1) and (0,0,0)→(0,0,−1)→(0,−1,−1,)→(−1,−1,−1) Either of these two sequences is selected depending upon a desired balancing state of the voltages of the DC terminals. Where the command vector is located at Sector 3, the vectors (1,0,0) and (0,−1,−1) indicate the same output voltages, but they reversely affect the voltages of the DC terminals. Using this property, the balance of the voltages of the DC terminals can be maintained by properly adjusting the ratio of time during which the voltages are supplied to the two vectors.
However, if a space vector pulse width modulation method is used to synthesize the command vectors, the calculation is very complicated, thereby giving a burden to a CPU. Further, according to the above-described method, since a continuous pulse width modulation method under which switching is performed at all the three phases is used, loss in switching is increased compared with a discontinuous pulse width modulation method. Where voltages are synthesized using a triangle pulse comparison method or the space vector pulse width modulation method, switching operations are generated at all the three phases within a control cycle, thereby increasing the switching loss as compared with the discontinuous pulse width modulation method.
In the DC terminals of the three-level inverter, since two condensers are connected in series with each other and the respective condensers are not connected to a constant voltage source, the voltages of the two condensers easily vary according to the current flowing at the neutral point of the DC terminals. In this case, distortion is generated in the output voltages, and stable operation of power devices cannot be assured.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made in view of the above shortcomings, and it is an object of the present invention to provide a pulse width modulation method of an inverter which can obtain a voltage balance between DC terminals and reduce the loss in switching, thereby permitting production of miniaturized and lightweight inverters.
This and other objects of the present invention may be achieved by a provision of a pulse width modulation method of a three-level inverter comprising a pair of condensers connected in series to each other, having a neutral point, and a plurality of switching devices, comprising the steps of obtaining effective offset voltages within an established control cycle of the inverter; calculating a switching loss in the switching devices according to each effective offset voltage supplied to the inverter; calculating a current flowing at the neutral point within the control cycle when each effective offset value is supplied; normalizing the calculated switching loss and the current flowing at the neutral point; and adding a predetermined weight to at least one of the normalized switching loss and the normalized neutral point current to select the offset voltage which the sum of the normalized switching loss and the normalized neutral point current is maximized.
Preferably, the switching loss calculation step comprises the sub-steps of obtaining a first loss difference between the maximum switching loss and the minimum switching loss; obtaining second loss differences between the maximum switching loss and the respective switching losses; and dividing each second loss difference by the first loss difference.
Preferably, the neutral point current calculation step comprises the sub-steps of obtaining a first current difference between the maximum current value and the minimum current value; obtaining second current differences between the maximum current value and the respective minimum current values; and dividing each second current difference by the first current difference.


REFERENCES:
patent: 5627742 (1997-05-01), Nakata et al.
patent: 5910892 (1999-06-01), Lyons et al.
patent: 6219265 (2001-04-01), Bernet et al.
patent: 6259616 (2001-07-01), Ekwall et al.

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