CMOS compatible SOI process

Details CMOS compatible SOI process CMOS compatible SOI process

2000-07-06

2001-12-04

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S658000, C438S660000

Reexamination Certificate

active

06326288

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of producing an IC circuit using a CMOS process, in particular a HV-CMOS process, wherein components are formed within troughs of different depths and of a first conductivity type, in particular N-type troughs, which are formed in a substrate layer of a second conductivity type opposite to the first conductivity type, in particular a P-type substrate.
BACKGROUND ART
Since the beginning of the nineties, publications on SOI processes are available that can roughly be grouped in two categories: thick-film SOI processes, in which the active silicon layer has a thickness distinctly greater than 1 &mgr;m, and thin-film SOI processes, where substantially thinner active silicon layers to below 100 nm are used.
Whereas in thin-film SOI processes the electrical properties of the components differ considerably from standard processes, thick-film SOI processes basically are more suitable therefor.
By insulating circuit portions and/or components on thick-film SOI material, e.g., by using trenches, i.e. vertical insulation layers provided in the depth of the silicon layer for the lateral insulation of functional portions on a chip, considerable advantages over standard technologies may be achieved:
parasitic effects such as latch-up are completely eliminated.
Minorities generated in power switches cannot cause interferences in adjacent circuit portions (e.g. logic circuit portions).
Free components, i.e. components uncoupled from the substrate, such as diodes, offer new possibilities in circuit design.
SUMMARY OF THE INVENTION
The invention is based on the principle idea of designing a SOI process (SOI=silicon on insulator) with a particularly simple process control, which is highly compatible with a standard CMOS process on standard silicon substrates. Here, the compatibility exists for both the process control and the electric behavior of the components.
The SOI process, wherein the substrate comprises a silicon layer disposed on an insulation layer, is intended to use advantages of the dielectric insulation of components and circuit portions for smart-power and high temperature applications.
It is desirable to apply a CMOS process, in particular a high voltage (HV) CMOS process, known per se, and therefore well controllable, to a so called bonded wafer, i.e. a SOI wafer. A bonded wafer comprises a top silicon layer in which the components are integrated. Below this silicon layer, an insulation layer, in particular of SiO, is arranged, underneath which a support layer is provided which, preferably, also is a silicon layer. This silicon wafer provided with the insulation layer is bonded to the support layer.
In a method for producing an integrated circuit using a CMOS process, in particular a HV CMOS process, components are formed within troughs of different depths and of a first conductivity type, in particular N-type troughs, which are formed in a substrate layer of a second conductivity type opposite to the first conductivity type, in particular a P-type substrate. Further, a SOI wafer substrate is used that comprises a top substrate layer for forming the CMOS components, a lateral insulation layer provided beneath the substrate layer, and a support layer arranged beneath the insulation layer. The top substrate layer has a thickness less than or equal to the greatest trough depth of the CMOS process. The top substrate layer is provided with trench insulation areas down to the subjacent lateral insulation layer, and components are formed within the areas of the silicon layer intermediate the trench insulation areas using the CMOS process, wherein the troughs of the greatest depth (high-voltage N-type trough) extend to the insulation layer and fill the respective area entirely, and wherein components are integrated directly in the troughs of the greatest depth (high-voltage N-type trough), whereas, for components requiring a lesser trough depth, the troughs (logic N-type trough) surrounding these components are provided in troughs of the greatest depth (high-voltage N-type trough).
The CMOS components produced on the SOI wafer substrate according to the present invention substantially behave like CMOS components formed in a standard substrate, if the conditions in the region below the components, i.e. in greater depths of the top substrate layer of the SOI wafer substrate do not vary substantially from the conditions in the standard substrate. This applies first to CMOS transistors that may be directly provided in the top substrate layer of the SOI wafer substrate without requiring any trough structures. Exemplary of a P-doped top SOI substrate layer are a high voltage NMOS (HV-NMOS) or a logic NMOS transistor. PMOS transistors, on the other hand, require an N-doped trough in the latter case. The depth of the N-type trough is greater for a HV-PMOS transistor than for a logic PMOS transistor. According to the present invention, the thickness of the top substrate layer of the SOI substrate is selected equal to the greater trough depth of the CMOS process. Thus, this wall extends directly to the insulation layer of the SOI wafer substrate, whereby the PN junction to the substrate, existing with a standard substrate, no longer exists. In the present invention, the deeper N-type trough located completely insulated in the SOI wafer substrate.
This N-type trough, as used for forming a HV-PMOS transistor in the SOI wafer substrate, may also be used to provide therein the shallower trough for a logic PMOS transistor. Again, the N-type trough of the PMOS transistor is insulated without a PN junction occurring in the depth of the SOI wafer substrate, since the deep N-type trough enclosing the shallow N-type trough for the logic PMOS transistor extends to the insulation layer of the SOI wafer substrate.
By matching the layer thickness of the top substrate layer of a SOI wafer substrate to the greatest trough depth of a CMOS process, it is possible to integrate CMOS components in the SOI wafer substrate, the behavior thereof substantially corresponding to the behavior of CMOS components integrated in a standard substrate. This is effected by the complete dielectric insulation of areas of different conductivity. To this end, it is necessary to completely insulate the troughs required for complementary elements, so as to avoid parasitic effects (e.g. bipolar effects). This leads to the thickness of the top substrate layer that must not be greater than the penetration depth of the troughs to be able to generate completely insulated areas of a complementary conductivity (see FIG.
3
). In particular, there is no need to alter the CMOS process to be able to apply it to a SOI wafer substrate.
Based on a standard CMOS process, the invention suggests the use of thick-film SOI wafer substrates and the introduction of a vertical insulation, in particular in the form of trench insulation, as a pre-process. After the vertical, e.g., trench insulation has been effected, the standard CMOS process is run unaltered.
The essential aspect of the invention is that, on the process level, the SOI process thus established differs from the standard CMOS process only in the basic material used and in the trench module as the pre-process. After the trench insulation has been effected, the standard CMOS process develops unmodified, being fully compatible with the process presently running on standard substrates. This offers considerable advantages regarding manufacturing logistics.
Concerning the compatibility of the components, a similar degree of identity can be expected. This offers the advantage that circuits produced with present technologies can readily be transferred to SOI technology.
Finally, it should be noted that the method suggested is not only applicable to standard CMOS processes but also to any semiconductor manufacturing process.


REFERENCES:
patent: 4578128 (1986-03-01), Mundt et al.
patent: 4740827 (1988-04-01), Niitsu et al.
patent: 5053350 (1991-10-01), Solomon
patent: 5313086 (1994-05-01), Jinbo
patent: 5382541 (1995-01-01), Bajor

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