Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1998-08-31
2001-05-22
Chan, Eddie P. (Department: 2183)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C710S005000, C710S052000, C711S150000
Reexamination Certificate
active
06237067
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
This invention pertains to memory coherency control. More particularly, it relates to a memory coherency control circuit utilizing a plurality of FIFO queues and a priority selection mechanism for avoiding deadlocks and assuring memory coherency.
2. Background Art
Memory controllers which maintain multiple queues to capture storage requests from processors and input/output (I/O) devices are required to enforce memory coherence rules which govern the order in which these requests access storage. The combinatorial logic designed to enforce these rules is complex and requires a considerable amount of circuitry to implement. Also, because of the complex nature of the design required to enforce these rules, the implementation is prone to errors, requiring additional hardware releases and inflating development costs.
Memory controller designs which include multiple queues to enforce storage coherency also can experience deadlock problems. Deadlocks can occur when two requests compete for the same resource, preventing further progress.
It is an object of the invention to provide an improved coherency control mechanism.
It is a further object of the invention to provide an improved coherency control mechanism which avoids deadlock conditions.
It is an object of the invention to reduce circuit complexity and the likelihood of design implementation error in a coherency control mechanism.
SUMMARY OF THE INVENTION
In accordance with the invention, memory coherency is controlled. Responsive to a request including a request type and request memory address, relevant queues are examined for queued addresses matching the request memory address. Responsive to a request memory address, matching at least one of the queued addresses, the request is rejected. Following a retry latency, the request is retried.
In accordance with a further aspect of the invention, when the address of a read request matches queued address in a store queue, at least one request in the store queue is prioritized higher than all other queued requests.
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Eberhard Raymond J.
Wong Eddie
Zeyak, Jr. Vincent P.
Beckstrand Shelley M.
Chan Eddie P.
International Business Machines - Corporation
Williams, II Jan S.
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