Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2000-03-02
2001-12-25
Butler, Dennis M. (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S152000, C713S600000
Reexamination Certificate
active
06334190
ABSTRACT:
TECHNICAL FIELD
This invention concerns a system for the manipulation of secure data which includes electronics or software, or both, that are designed to operate within a specific clock speed range.
BACKGROUND OF THE INVENTION
The process of authentication has particular application in any system (chip or software) that manipulates secure data. This includes Internet commerce, peer to peer communication, Smart Cards, Authentication chips, electronic keys, and cryptographic equipment. Whilst the description of the preferred embodiments of the present invention assumes a System/consumable relationship, it is a trivial matter to extend the protocol for other uses. An example is Internet commerce, where each consumer is effectively the consumable, and the Shop is the System. Another usage is Smart Cards, where each smart card can have a unique key, known to the System.
Existing solutions to the problem of authenticating consumables have typically relied on physical patents on packaging. However this does not stop inferior refill operations or clone manufacture in countries with weak industrial property protection. Consequently a much higher level of protection is required.
SUMMARY OF THE INVENTION
This invention is a system for the manipulation of secure data. The system includes electronics or software, or both, that are designed to operate within a specific clock speed range. The system is also provided with a clock frequency limiter in the clock signal line, upstream of elements that are to be protected. The limiter involves an enable gate having an input port, an output port and a control port, and is located in the clock signal line to pass the clock signal from the input port to the output port only when it is enabled by a signal at the control port. Clock signal taps are connected to pass clock signals from upstream and downstream of the enable gate to an edge detector, and the output of the edge detector is passed through a delay to the control port of the enable gate
This arrangement limits the speed of the clock arriving at the elements to be protected and therefor prevents the introduction of race conditions into the elements during processing. For instance, a high clock speed (higher than the circuitry is designed for) may prevent an XOR from working properly, and of the two inputs, the first may always be returned. These styles of transient fault attacks can be very efficient at recovering secret key information. The delay may be set so that the maximum clock speed is a particular frequency, such as about 4 MHz. Note that this delay is not programmable—it is fixed. The filtered clock signal may be further divided internally as required.
The clock frequency limiter may be implemented in CMOS, and it may be covered by both tamper detection and prevention lines.
REFERENCES:
patent: 4801935 (1989-01-01), Cairns
patent: 5810146 (1998-09-01), Harbaugh
patent: 5864695 (1999-01-01), Yanagihara
patent: 6217165 (2001-04-01), Silverbrook
Silverbrook Kia
Walmsley Simon Robert
Butler Dennis M.
Silverbrook Research PTY Ltd.
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