Method of forming a node contact of a DRAM's memory cell

Details Method of forming a node contact of a DRAM's memory cell Method of forming a node contact of a DRAM's memory cell

1999-09-08

2001-02-13

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S639000, C438S640000

Reexamination Certificate

active

06187669

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a node contact of a DRAM's (dynamic random access memory) memory cell on a semiconductor wafer, and more particularly, to a method of forming a node contact for forming an electrical terminal for connecting the bottom electrode of a capacitor in the memory cells.
2. Description of the Prior Art
A memory cell of a stacked DRAM comprises a transistor and a capacitor stacked on the transistor. The stacked DRAM employs the transistor as a switch of a bit line that reads data stored in the capacitor. A conductor inside a node contact forms an electrical terminal for electrically connecting the bottom electrode of a capacitor with the transistor. The node contact passes through the space between two bit lines in the pattern design of the semiconductor wafer. As the space of two bit lines becomes smaller, a short circuit between the conductor inside the node contact and the neighboring bit lines is more likely to occur, which may result in losing the data stored in the capacitor. The fabrication of a node contact for electrically connecting the bottom electrode of the capacitor and for isolating the conductor inside the node contact via to prevent it from contacting the neighboring bit lines is an important subject in the semiconductor process.
Please refer to
FIG. 1
to
FIG. 6
, which are schematic diagrams of the prior art method of forming the node contact
48
.
FIG. 1
is a top view of a prior art semiconductor wafer
10
.
FIG. 2
is a sectional view along line
2
—
2
of the semiconductor wafer
10
shown in FIG.
1
.
FIG. 3
is a sectional view along line
3
—
3
of the semiconductor wafer
10
shown in FIG.
1
.
FIG. 4
is a top view of a prior art node contact
48
.
FIG. 5
is a sectional view along line
5
—
5
of the semiconductor wafer
10
shown in FIG.
4
.
FIG. 6
is a sectional view along line
6
—
6
of the semiconductor wafer
10
shown in FIG.
4
. The method of forming a prior art node contact
48
takes place on a semiconductor wafer
10
. As shown in
FIG. 1
to
FIG. 3
, the semiconductor wafer
10
comprises a substrate
12
, a dielectric layer
14
, a first bit line
16
and a second bit line
18
. Each of the first and the second bit lines
16
and
18
has a rectangular cross section and two vertical side walls. The first side wall of the first bit line
16
comprises a first region
15
and two second regions
17
adjacent to the first region
15
. The distance d
1
between the first region
15
and the second side wall
19
is greater than a predetermined value, and the distance d
2
between the two second regions
17
and the second side wall
19
is less than the predetermined value.
The method of forming the node contact
48
according the prior art begins with forming a second dielectric layer (not shown) on the vertical side walls of the first bit line
16
and the second bit line
18
. The second dielectric layer forms a spacer
30
surrounding the vertical side walls of the first bit line
16
and the second bit line
18
. The distance d
1
between the first region
15
and the second side wall
19
of the second bit line
18
is larger, and the distance d
2
between the two second regions
17
of the first bit line
16
and the second side wall
19
of the second bit line
18
is smaller. Thus, a groove
32
with a larger opening is formed over the gap between the two spacers
30
of the first region
15
and the second side wall
19
, and a gap
34
with a high aspect ratio is formed over the gap between the two spacers
30
of the second region
17
and the second side wall
19
.
As shown in
FIG. 4
to
FIG. 6
, a third dielectric layer
40
is formed on the semiconductor wafer
10
to fill the groove
32
. A lithography process is then employed to form a photo-resistance layer (not shown) with a hole to define the position of the node contact. Then, an anisotropic etching process without removing the spacer
30
is performed to remove the third dielectric layer
40
and the first dielectric layer
14
under the hole of the photo-resistance layer in a vertical direction and form a node contact
48
. And then the photo-resistance layer is removed to complete the formation of the node contact
48
. During the formation of the third dielectric layer
40
, the third dielectric layer
40
can't completely fill the gap
34
because of its high aspect ratio. As a result, a pipe (void)
42
is formed between the two spacers
30
of the second region
17
and the second side wall
17
.
Please refer to
FIG. 7
to
FIG. 9
, which are schematic diagrams of the formation the polysilicon layer
50
inside the node contact
48
according to the prior art.
FIG. 7
is a top view of the polysilicon layer
50
formed inside the node contact
48
shown in FIG.
9
.
FIG. 8
is a sectional view along line
8
—
8
of the semiconductor wafer
10
shown in FIG.
7
.
FIG. 9
is a sectional view along line
9
—
9
of the semiconductor wafer
10
shown in FIG.
7
. After the formation of the node contact
48
, a polysilicon layer
50
which fills the node contact
48
is formed to be used as an electrical terminal for connecting the transistor of the semiconductor wafer
10
and the bottom electrode of the subsequent fabricated capacitor. However, due to the connection between the node contact
48
and the pipe
42
under the third dielectric layer
40
, it is easy to fill the pipe
42
with the polysilicon layer
50
during the formation of the polysilicon layer
50
inside the node contact
48
. The polysilicon layer
50
inside the pipe
42
results in forming a leakage path between each of the capacitors in the subsequent electrical connection processes. In
FIG. 7
, the arrow
52
shows the direction of the leakage path.
In the prior art method of forming the node contact
48
, the pipe
42
is formed, leading to the formation of the polysilicon layer
50
inside the pipe
42
when forming the polysilicon layer
50
inside the node contact
48
. Although the node contact
48
is surrounded by the dielectric layer
14
to isolate the polysilicon layer
50
from contacting the first bit line
16
and the second line
18
, the polysilicon layer
50
inside the pipe
42
forms the leakage path between each capacitor resulting in losing the data by changing the number of the charges stored in the capacitor.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a node contact with self-alignment to prevent the formation of the leakage path between each capacitor.
In a preferred embodiment, the present invention provides a method of forming a node contact of a DRAM's memory cell on a semiconductor wafer, the semiconductor wafer comprising a substrate, a dielectric layer positioned on the substrate, and a first bit line and a second bit line positioned on the dielectric layer, each of the two bit lines having two vertical side walls and a rectangular cross section, and comprising a conductive layer on the dielectric layer with an overlying first insulating layer wherein a first side wall of the first bit line is adjacent to a second side wall of the second bit line and the first side wall comprises a first region and two second regions adjacent to the first region, the distance between the first region and the second side wall being greater than a predetermined value and the distance between the two second regions and the second side wall being less than the predetermined value; the method comprising:
forming a second insulating layer on the dielectric layer and the two bit lines which fills the gap between each of the two second regions and the second side wall and partially fills the gap between the first region and the second side wall which forms a groove over the gap between the first region and the second side wall;
performing a first anisotropic etching process to completely remove the second insulating layer above the two bit lines and to extend the bottom of the groove bet

Affiliated with

Also associated with

Rating

Method of forming a node contact of a DRAM's memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming a node contact of a DRAM's memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a node contact of a DRAM's memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2563630