Semiconductor memory, memory device, and memory card

Details Semiconductor memory, memory device, and memory card Semiconductor memory, memory device, and memory card

1999-10-26

2001-07-24

Moise, Emmanuel L. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S054000, C714S763000, C365S195000, C365S201000

Reexamination Certificate

active

06266792

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field to which the Invention Belongs
The present invention relates to an art making it possible to achieve complete compatibility with a non-defective semiconductor memory by combining semiconductor memories having irremediable local defects, particularly to an art for constituting a memory device or a memory card by combining a plurality of flash memories having irremediable defects which can be apparently ignored.
2. Technical Background of the Invention
When some of the memory cells in a semiconductor memory are defective, it is possible to repair the semiconductor memory by replacing the defective memory cells with redundant memory cells. However, when a malfunctioning portion of a semiconductor memory exceeds a remediable range, the semiconductor memory is regarded as defective. A semiconductor memory having no malfunctioning portion or whose malfunctioning portion is in a remediable range is referred to as a complete composite conforming circuit. The defective product can be used as an operable product by removing defective portions from the memory and decreasing the entire memory capacity of the memory to ½ or ¼. This locally operable product is a partial product. Partial products can be used by mutually combining partial products in which the operable portion of one partial product compensates the inoperable portion of the other product. For example, in the case of a low-order partial product, in which the high-order half of the memory area is defective, and a high-order partial product, in which the low-order half of the memory area is defective, it is possible to use these partial products in combination by fixing the address input terminal of an address bit provided to select the high order or low order portion of the memory area to the selection level of a low-order side memory area at the outside, in the case of the low-order partial product, and fixing the address input terminal of an address bit provided to select the high order or low order portion of the memory area at the outside in the case of a high-order partial product.
When the data input/output terminals of the high-order partial product and low-order partial product are connected to each other in common at the outside to use the partial products instead of a non-defective product, chip selection must be performed for each partial product by using different chip selection signals. Therefore, to use a partial product for a semiconductor memory in a memory card, it is necessary to increase the number of chip selection signals compared to the case where a non-defective product is used, and moreover, it is necessary to use a decoder having different logic for chip selection when using a partial product in comparison to that a non-defective product.
Moreover, each defective portion of a plurality of partial products may have a difference depending on the fabrication process. When combining a plurality of partial products in which defective-portion tail address regions are complementary instead of using a non-defective product, if the partial products having different defective portions are biased in quantity, a larger portion of the partial products are left unused.
Furthermore, in the case of a nonvolatile semiconductor memory, such as a flash memory, rewriting of information is performed by bringing the memory cells into an erasing state and then data write is performed. Also, a verify operation is necessary for the erase and write operations. In the case of a semiconductor memory, such as a flash memory, erase, erase verify, write, and write verify operations are controlled inside the memory so that data can be written even on the system (on-board state). The state in which a rewrite operation is performed inside is reported to an access body, such as a microprocessor, in accordance with, for example, a ready/busy signal. When a failure occurs in the erase operation or write operation due to deterioration of the characteristics of a memory cell, an erase state or write state necessary for the memory cell cannot be obtained even if the erase and erase verify operations and write and write verify operations are repeated many times and the internal rewrite control operation is abnormally ended.
It is an object of the present invention to provide a semiconductor memory which directly applicable to a memory device and a memory card by using a plurality of partial products instead of a non-defective product or complete composite conforming circuit.
It is another object of the present invention to provide a semiconductor memory which is capable of preventing a contradiction of the internal states from occurring between a partial product in which the operation of its defective portion is designated by an access from an external unit and another partial product substituted for the former partial product, and, moreover, to provide a memory device using the memory.
It is still another object of the present invention to provide a semiconductor memory which is capable of changing the address arrangement of an operable portion separated from a defective portion irrespective of built-in address decoding logic, and, moreover, to provide a memory device using the memory.
It is still another object of the present invention to provide a memory card which is capable of using an address decoding logic for chip selection for a semiconductor memory in common with a case where a complete composite conforming circuit is used even when a partial product is used.
The above and other objects and novel features of the present invention will become more apparent from the description provided in this specification and the accompanying drawings.
SUMMARY OF THE INVENTION
Semiconductor memories (
1
,
1
C) of the present invention include a plurality of memory blocks (
2
,
3
or
2
Y,
3
Y) constituted by a plurality of memory cells, a data input/output buffer (
7
) to which data to be written in the memory blocks is supplied and which outputs the data read out of the memory blocks to an external unit, and first control means for controlling the rewriting of data into and the reading of data from the memory cells. The first control means is denoted by symbol
11
in FIG.
1
and by symbols
43
Y,
45
, and
46
Y in FIG.
31
. The semiconductor memories are provided with first storage means (
30
,
47
) for designating defective memory blocks included in the above memory blocks and detection means (
32
,
48
Y) for detecting the access to the defective memory blocks designated by the first storage means in accordance with an address signal. In this case, when the detection means detects an access to the defective memory blocks, the control means inhibits a data rewrite operation in the case of a data rewrite operation and inhibits a data output operation of the data input/output buffer in the case of a data read operation.
Moreover, semiconductor memories (
1
,
1
B, or
1
C) according to another aspect of the present invention include a plurality of memory blocks (
2
,
3
or
2
Y,
3
Y) constituted by a plurality of electrically erasable memory cells, a data input/output buffer (
7
) to which data to be written in the memory blocks is supplied from an external unit and which outputs data read out of the memory blocks to an external unit, and first control means for controlling the writing of data into and the reading of data from the memory cells. The first control means is denoted by symbol
11
in
FIG. 1
, and by symbols
43
,
44
,
45
, and
46
in FIG.
15
and by symbols
43
Y,
45
, and
46
in FIG.
31
. The semiconductor memories are provided with first storage means (
30
,
47
) for designating defective memory blocks included in the above memory blocks and detection means (
32
,
48
,
48
Y) for detecting an access to the defective memory blocks designated by the first storage means in accordance with an address signal. The control means is set to a status (MR/B) representing the completion of the data rewrite operation in the case of a data rewrite operation when the d

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