SRAM cell having overlapping access transistor and drive...

Details SRAM cell having overlapping access transistor and drive... SRAM cell having overlapping access transistor and drive...

1999-10-06

2001-10-16

Williams, Alexander O. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S903000, C257S904000, C257S907000, C257S379000, C257S067000, C257S068000, C257S385000, C365S154000, C365S182000

Reexamination Certificate

active

06303966

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for fabricating the same, and more particularly, to an SRAM (Static Random Access Memory) cell and a method for fabricating the same.
2. Discussion of the Related Art
In general, the SRAM cell consists either four transistors (for example, 2 access transistors and 2 drive transistors) and 2 polysilicon load resistors or 6 transistors. In particular, a highly integrated cell of 4 M class and over has 6 transistors in the form of CMOS including, in general, 4 NMOS transistors and 2 PMOS transistors. In an SRAM cell of lower integration, an asymmetrical cell is used, which is favorable in view of the occupied area. As the cell becomes highly integrated with a reduction of the occupied area, in which the asymmetry significantly affects the performance of the cell, a symmetrical cell becomes essential. However, with symmetry, a bit area becomes larger for the same line width Accordingly, a current major interest is to reduce the area while maintaining the symmetry.
FIG. 1
illustrates an equivalent circuit of a conventional CMOS SRAM cell. As shown, the conventional SRAM cell includes 4 NMOS transistors Q
1
~Q
4
formed on a semiconductor substrate and 2 PMOS transistors Q
5
and Q
6
formed on the NMOS transistors as thin film transistors.
A conventional method for fabricating the SRAM cell having the aforementioned system will be explained with reference to the attached drawings.
FIG. 2
a
illustrates a plan view showing an arrangement of bulk transistors in the conventional SRAM cell.
FIG. 2
b
illustrates a plan view showing an arrangement of thin film transistors in the conventional SRAM cell.
FIG. 3
illustrates a plan view showing an arrangement of the thin film transistors in
FIG. 2
b
over the bulk transistors in
FIG. 2
a
in the conventional SRAM cell.
FIG. 4
illustrates a section of the conventional SRAM cell across a line IV—IV in FIG.
3
.
FIG. 5
illustrates a section of the conventional SRAM cell across a line V—V in FIG.
3
.
Referring to the drawings, in the conventional method for fabricating an SRAM, a semiconductor substrate
31
is provided, and active regions
32
and field regions
32
a
are defined on the semiconductor substrate
31
. A first gate oxide film
33
is formed on each of the active regions
32
. A first polysilicon and a cap gate nitride film
34
are formed in succession on the first gate oxide film
33
and photoetched to define a first gate electrode
35
of a bulk transistor. Sidewall oxide films
37
are formed on both sides of the first gate electrodes
35
. The first gate electrode
35
and the sidewall oxide films
37
on both sides thereof are used as masks in injecting impurity ions to form first and second impurity regions
39
and
41
in the active regions
32
. A first interlayer insulating film
43
is formed on the entire surface over the semiconductor substrate
31
and etched to open a predetermined portion of the semiconductor substrate
31
. A second polysilicon is deposited on the first interlayer insulating film
43
to be in contact with the first impurity region
39
to form a Vss line
44
. Then, a second interlayer insulating film
45
and a third polysilicon are formed in succession on the Vss line
44
. The third polysilicon is patterned with a photo-etching process to form a second gate electrode
46
of the thin film transistor. A second gate oxide film
47
and fourth polysilicon are formed on the semiconductor substrate
31
, and an offset mask
48
is covered thereon. P type impurities are doped on the offset mask
48
to form a body
49
of a thin film transistor having source, drain and channel regions. In order to improve a transistor performance, heat treatment is carried out to increase the grain sizes. The SRAM cell is completed when processed through exposure, etching, and wiring. That is, an insulating film
50
is formed on the entire surface inclusive of the body
49
of the thin film transistor, and a contact hole to expose a surface of the first impurity region
39
is formed. Then, a metal wiring
51
is formed on the entire surface inclusive of the contact hole.
However, the aforementioned conventional SRAM cell and method for fabricating the same have the following problems. First, the asymmetry of the drive transistors and access transistors places a limitation on the reduction of a cell size. Second, the difference in the channel directions of the drive transistors and access transistors complicates the fabrication process of the memory cell. Third, the spaced formation with certain intervals and a connection of the gates to one another in a later fabrication process of the access transistors causes the cell to have a larger area.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an SRAM cell and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the invention is to provide an SRAM cell having a small cell size.
Another object of the invention is to provide an SRAM cell having a less complicated fabricating process.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the SRAM cell having first and second access transistors, first and second drive transistors and first and second load resistors, wherein a first terminal of the first access transistor, a gate terminal of the second drive transistor and a first load resistor terminal are connected to one another to form a first cell node terminal, and a first terminal of the second access transistor, a gate terminal of the first drive transistor and a second load resistor terminal are connected to one another to form a second cell node terminal, the SRAM cell includes a gate electrode of each of the first, and second drive transistors arranged over a semiconductor substrate in a first direction, and a gate electrode of each of the first, and second access transistors arranged in the first direction overlapped with portions of the gate electrodes of the first, and second drive transistors.
In another aspect of the present invention, there is provided a method for fabricating an SRAM cell, the SRAM cell having first and second access transistors, first and second drive transistors and first and second load resistors, wherein a first terminal of the first access transistor, a gate terminal of the second drive transistor and a first load resistor terminal are connected to one another to form a first cell node terminal, and a first terminal of the second access transistor, a gate terminal of the first drive transistor and a second load resistor terminal are connected to one another to form a second cell node terminal, the method including the steps of forming the first, and second drive transistors each having impurity regions and a gate, forming the first, and second access transistors each having impurity regions and gates formed overlapped with portions of, and in parallel to gates of the first, and second drive transistors, forming an insulating film having contact holes to the impurity regions of the first, and second drive transistors, and forming the first, and second load resistors on the insulating film connected to the impurity regions of the first, and second drive transistors.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


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