Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-03-16
2001-07-10
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S657000, C438S637000
Reexamination Certificate
active
06258708
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a multi-layered wiring structure and a method of fabricating the same.
Description of the Related Art
FIGS. 1A
to
1
F are cross-sectional views of a semiconductor device, illustrating respective steps of a conventional method of fabricating a semiconductor device such as SRAM.
As illustrated in
FIG. 1A
, a silicon dioxide film
2
is formed on a semiconductor substrate
1
by a thickness in the range of 200 nm to 500 nm. The silicon dioxide film
2
defines device formation regions surrounded therewith where a semiconductor device is to be formed. Then, a silicon dioxide film as a gate oxide film
3
is formed on the semiconductor substrate
1
in the device formation regions by a thickness in the range of 4 nm to 10 nm. Then, a polysilicon film and a refractive silicide film are deposited over the product by a total thickness in the range of 50 nm to 300 nm. This multi-layered structure will make a gate electrode or a first wiring layer. Then, a silicon nitride film
5
is deposited over the multi-layered structure by a thickness in the range of 50 nm to 200 nm.
A patterned photoresist (not illustrated) is formed on the silicon nitride film
5
, and then, the silicon nitride film
5
is etched by using the patterned photoresist as a mask. Subsequently, the multi-layered structure of the polysilicon film and the refractive silicide film is etched to thereby form a gate electrode layer
4
. Then, a sidewall
6
made of silicon nitride is formed around both the silicon nitride film
5
and the gate electrode layer
4
. Then, a first interlayer insulating film
7
is deposited entirely over the product.
FIG. 1A
illustrates the thus formed intermediate product.
Then, as illustrated in
FIG. 1B
, a patterned photoresist
10
B is formed on the first interlayer insulating film
7
, followed by anisotropic etching to thereby form a shared contact hole
8
. The thus formed shared contact hole
8
reaches both the gate electrode layer
4
and the semiconductor substrate
1
.
After removal of the photoresist
10
B, a polysilicon or SIPOS film
11
as a second wiring layer is deposited over the product by a thickness in the range of 20 nm to 100 nm. SIPOS is an abbreviation of “semi-insulating polycrystalline silicon”, and means a mixture of SiH
4
and N
2
O usually synthesized by chemical vapor deposition (CVD). SIPOS is usually used for forming a highly resistive load element. After the formation of the polysilicon or SIPOS film
11
, a patterned photoresist
12
B is formed on the polysilicon or SIPOS film
11
, as illustrated in FIG.
1
C.
Then, the polysilicon or SIPOS film
11
is anisotropically etched with the patterned photoresist
12
B acting as a mask, to thereby form a resistive layer
14
and Vcc wiring layer
13
, as illustrated in FIG.
1
D. The resistive layer
14
covers an inner surface of the first contact hole
8
therewith, and makes contact with both the gate electrode layer
4
and the semiconductor substrate
1
. The Vcc wiring layer
13
is located above the gate electrode layer
4
.
After removal of the patterned photoresist
12
B, a second interlayer insulating film
16
is deposited over the product. Then, as illustrated in
FIG. 1D
, a patterned photoresist
17
B is formed over the second interlayer insulating film
16
, followed by anisotropic etching of the first and second interlayer insulating films
7
and
16
, and the silicon nitride film
5
by using the patterned photoresist
17
B as a mask, to thereby form a second contact hole
19
B. As illustrated in
FIG. 1D
, the second contact hole
19
B reaches the gate electrode
4
.
After removal of the patterned photoresist
17
B, another patterned photoresist
17
C is formed over the second interlayer insulating film
16
. Then, the first and second interlayer insulating films
16
and
7
are partially removed by anisotropic etching with the patterned photoresist
17
C used as a mask, to thereby form a third contact hole
18
, as illustrated in
FIG. 1E. A
diffusion layer (not illustrated) formed in the semiconductor substrate
1
is exposed to the thus formed third contact hole
18
. The etching for forming the third contact hole
18
is carried out with a selection ratio to the silicon nitride films
5
and
6
being sufficiently great. Hence, even if the third contact hole
18
overlapped the gate electrode
4
, a short-circuit can be prevented between the gate electrode layer
4
and a later mentioned contact plug formed in the third contact hole
18
, because the gate electrode
4
is entirely covered with the silicon nitride films
5
and
6
.
Then, as illustrated in
FIG. 1F
, after removal of the photoresist
17
C, the second contact hole
19
B and the third contact hole
18
are filled with tungsten to thereby form tungsten plugs
20
therein. Then, a patterned aluminum wiring layer
21
as a third wiring layer is formed on the second interlayer insulating film
16
, making contact with the tungsten plugs
20
, as illustrated in FIG.
1
F.
In the above-mentioned method of fabricating a semiconductor device, the silicon nitride film
5
is formed on the gate electrode layer
4
for preventing a short-circuit between the contact plug
20
and the gate electrode layer
4
, in order to form the contact plug
20
located above the diffusion layer in self-aligned manner against the gate electrode layer
4
. Accordingly, the second contact hole
19
B reaching the gate electrode layer
4
has to be formed independently of the third contact hole
18
reaching the semiconductor substrate
1
above the diffusion layer. This causes the requisite number of masks to increase, which in turn causes an increase in fabrication costs and a reduction in fabrication yield.
Another semiconductor device layout has been suggested by S. Horiba et al., “A Symmetric Diagonal Driver Transistor SRAM Cell with Imbalance Suppression Technology for Stable Low Voltage Operation”, 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 144-145. There has been suggested a symmetric diagonal driver transistor (SDDT) cell for low voltage SRAM operation which exhibits high alignment tolerance. This symmetric cell layout is said to substantially suppress the imbalance in a pair of cell transistor characteristics.
SUMMARY OF THE INVENTION
In view of the foregoing problems of the conventional methods of fabricating a semiconductor device, it is an object of the present invention to provide a method of fabricating a semiconductor device, which is capable of preventing the number of masks to be used from being increased, and hence enhancing a fabrication yield by making it possible to concurrently form a contact hole reaching a gate electrode and a contact hole reaching a diffusion layer when contact holes are to be formed in self-aligned fashion. It is also an object of the present invention to provide a semiconductor device capable of doing the same.
In one aspect of the present invention, there is provided a method of fabricating a semiconductor device, including the steps of forming a first wiring layer on a semiconductor substrate, the first wiring layer being covered therearound with an insulating film, forming a first interlayer insulating film over the product resulting from the previous step, simultaneously forming a first contact hole reaching the semiconductor substrate and a second contact hole reaching the first wiring layer, forming a second wiring layer over the product resulting from the previous step, forming a second interlayer insulating film over the product resulting from the previous step, simultaneously forming a third contact hole reaching the semiconductor substrate and a fourth contact hole reaching the second wiring layer, and forming a third wiring layer over the third and fourth contact holes.
The first contact hole may reach the first wiring layer as well as the semiconductor substrate. For instance, the s
Chaudhuri Olik
Hutchins, Wheeler & Dittmar
NEC Corporation
Rao Shrinivas H.
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