Process for low-k dielectric with dummy plugs

Details Process for low-k dielectric with dummy plugs Process for low-k dielectric with dummy plugs

1999-01-11

2001-07-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S629000, C438S637000, C438S778000, C438S780000, C438S787000, C257S751000, C257S758000

Reexamination Certificate

active

06258715

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to methods of fabricating a semiconductor wafer, and more particularly to methods of thermal stress release by providing dummy plugs in a low-k, low thermal conductivity dielectric.
2. Description of the Related Art
Materials used for intermetal dielectrics (IMDs) in the related art comprise plasma enhanced silicon oxide (PE-OX), plasma enhanced tetraethyl orthosilicate glass (PETEOS), spin-on-glass (available from Allied Signal as #314), low-k dielectric (Dow-Corning FO
X
-15), and others. Along with their advantages come certain disadvantages such as the problem of moisture uptake (through etching) and release, contributing to bonding failure or poor thermal conductivity in case of the low-k dielectric.
FIG. 1
illustrates a typical IMD arrangement of the prior art, and having the problems discussed in the previous paragraph, showing a partial cross-section of a semiconductor wafer
10
. Reference number
11
indicates the top of the wafer, with a bonding pad
12
on top of
11
. A metal plug
13
connects the bonding pad
12
to a metal line (not shown). A PE-OX or PETEOS layer
14
is deposited on top of a SOG or low-k dielectric layer
15
. Layer
15
in turn is deposited on a liner PE-OX layer
16
.
In ultra-large-scale-integration (ULSI) interconnect scaling has become the performance limiting factor for new designs. Both interconnect resistance and capacitance are limiting factors to overall performance. To minimize crosstalk and RC time delay it is very important to keep the inter-metal dielectric capacitance as low as possible. This has been done through the introduction of inter-metal dielectrics (IMD's) with a low dielectric constant (low-k) such as hydrogen silsesquioxane (HSQ) and methyl silsesquioxane (MSQ). One drawback of these materials is that their thermal conductivity is not as good as that of regular oxides such as silicon oxide (SiO
2
). The reduced thermal conductivity of these low-k insulators introduces thermal stress during chip bonding, because the local temperature around bonding pads is then especially high. This thermal stress may cause delamination of inter-metal dielectric and metallization layers.
One method to alleviate the poor thermal conductivity is to introduce “dummy plugs” made of various thermally conductive materials, which transfer the excessive heat around the bonding pads and distribute it to other layers of the semiconductor wafer. Another problem faced with low-k IMDs is that their adhesion to oxides is worse than that of oxide to oxide. Dummy plugs alleviate this problem by tying the IMD layer to the other layers.
The use of dummy pads is not new in the manufacture of semiconductor chips. There are a number of U.S. patents that describe their use and which are listed below.
U.S. Pat. No. 5,629,236 (Wada et al.) shows a method of converting polycrystal A
1
wiring to single crystal A
1
(connected by vias) to reduce electromigration. A dummy plug is used to supply atoms to reduce electromigration.
U.S. Pat. No. 5,430,325 (Sawada et al.) describes a chip having a dummy pattern. The dummy pattern reduces recognition errors.
U.S. Pat. No. 5,319,224 (Sakashita et al.) teaches a method for a bond pad layout.
It should be noted that none of the above cited examples of the related prior art address alleviating the poor thermal conductivity and adhesion problems of HSQ and MSQ.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide methods to improve thermal conductivity and to reduce the resulting thermal stress and subsequent delamination, when using low-k, low thermal conductivity silsesquioxane inter-metal dielectric layers in the manufacture of semiconductor wafers.
Another object of the present invention is to improve the adhesion of these low-k inter-metal dielectric layers to other types of oxide layers.
A further object of the present invention is to improve the removal of moisture taken up during the etching step.
These objects have been achieved by providing heat transferring metal dummy plugs under and/or outside bonding pads, placing dummy plugs in bonding pad areas that are unused, and by providing dummy plugs between any two metallization layers. Dummy plugs also provide increased mechanical strength by tying together the different types of layers encountered in a semiconductor wafer.


REFERENCES:
patent: 5319224 (1994-06-01), Sakashita et al.
patent: 5430325 (1995-07-01), Sawada et al.
patent: 5580810 (1996-12-01), Katto et al.
patent: 5629236 (1997-05-01), Wada et al.
patent: 5855962 (1999-01-01), Cote et al.
patent: 6016000 (2000-01-01), Moslehi et al.
patent: 6016600 (2000-01-01), Moslehi

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