Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1999-03-22
2001-05-22
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S117000, C711S118000, C711S131000, C711S156000, C711S168000, C710S039000, C710S052000, C712S009000
Reexamination Certificate
active
06237066
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to the design of computer systems. More specifically, the present invention relates to the design of a load store unit for a computer system that supports simultaneous outstanding requests to multiple targets.
2. Related Art
Recent processor designs achieve high performance by operating multiple pipelined functional units in parallel. This allows more than one computational operation to complete on a given clock cycle. In order to keep pace with such processor designs, memory systems have been modified to allow pipelining of memory accesses. This allows memory access requests to be issued before prior memory accesses return, which can greatly increase memory system throughput.
However, if a computer program changes sources of data (targets) during program execution, such pipelined memory systems typically stall, which can greatly degrade system performance. For example, if a program makes an access to a graphics co-processor in between pipelined accesses to main memory, the accesses to main memory will stall. This can be a significant problem for processor designs that support interleaved accesses to many different sources of data (targets). For example, a given processor may be able to access data from a data cache, a main memory, a graphics co-processor and from a variety of bus interfaces.
Furthermore, such pipelined memory systems typically issue at most one access request on a given clock cycle, which can limit performance in situations where multiple requests are simultaneously generated by multiple pipelined functional units, or when multiple requests have been accumulated in a buffer due to resource conflicts.
What is needed is a memory system design that overcomes these performance limitations of existing memory systems.
SUMMARY
One embodiment of the present invention provides an apparatus that supports multiple outstanding load and/or store requests from an execution engine to multiple sources of data in a computer system. This apparatus includes a load store unit coupled to the execution engine, a first data source and a second data source. This load store unit includes a load address buffer, which contains addresses for multiple outstanding load requests. The load store unit also includes a controller that coordinates data flow between the load address buffer, a register file and the first data source and the second data source so that multiple load requests can simultaneously be outstanding for both the first data source and the second data source. According to one aspect of the present invention, the load store unit additionally includes a store address buffer, that contains addresses for multiple outstanding store requests, and a store data buffer that contains data for the multiple outstanding store requests. The controller is further configured to coordinate data flow between the first data source, the second data source, the store address buffer and the store data buffer, so that multiple store requests can simultaneously be outstanding for both the first data source and the second data source.
According to one aspect of the present invention, the load store unit is additionally coupled to a third data source, and the controller is configured to coordinate data flow so that multiple load requests can simultaneously be outstanding for the third data source.
According to one aspect of the present invention, the load store unit is coupled to the first data source, which is a data cache, through a first communication pathway, and is coupled to the second data source through a second communication pathway that is separate from the first communication pathway.
According to one aspect of the present invention, the controller is configured so that load requests return in-order from the second data source, but can return out-of-order from the first data source.
According to one aspect of the present invention, the controller is configured so that multiple load requests can be sent to different data sources in the same clock cycle.
According to one aspect of the present invention, the controller includes a separate state machine for each entry in the load address buffer.
According to one aspect of the present invention, the second data source includes one of, an interface to a computer system bus, a random access semiconductor memory, a secondary storage device, and a computer graphics accelerator.
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Pan Bi-Yu
Tremblay Marc
Nguyen Hiep T.
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
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