Semiconductor memory device having column selection circuit acti

Details Semiconductor memory device having column selection circuit acti Semiconductor memory device having column selection circuit acti

1991-07-17

1994-04-19

Heyman, John S.

Static information storage and retrieval

Read/write circuit

Signals

365201, 365233, G11C 700

Patent

active

053052650

ABSTRACT:
The semiconductor memory device according to the present invention has a memory cell array which includes a plurality of memory cells provided in array form and a plurality of bit lines and word lines that are respectively connected to the memory cells, where the bit lines are arranged so as to form a group of paired lines, sense amplifiers which are provided one for each of the bit line pairs, for amplifying the potential difference between the lines of the bit line pair in response to an activating signal, a delay circuit which uses said activating signal as its input signal, for generating a selection signal by giving to said activating signal a delay time that varies in response to a control signal from a switching circuit, and selection switch means for connecting a predetermined one of said bit line pairs and I/O lines in response to said selection signal.
When a read error is detected by a function test, the switching circuit is set so as to generate an active level control signal DS, when the read error is eliminated by the setting, it is possible by setting the switching circuit so as to permanently fix the control signal to the active level to convert articles that had to be classified as defective conventionally to conforming articles, thereby making it possible to contribute to an enhancement of the yield.

REFERENCES:
patent: 4656612 (1987-04-01), Allan
patent: 4687951 (1987-08-01), McElroy
patent: 4748595 (1988-05-01), Mattausch
patent: 5023840 (1991-06-01), Tobita
patent: 5033026 (1991-07-01), Tsujimoto
patent: 5051995 (1991-09-01), Tobita

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