Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1998-11-09
2001-10-09
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S238000, C438S239000, C438S253000
Reexamination Certificate
active
06300213
ABSTRACT:
TECHNICAL FIELD
This invention relates to semiconductor processing methods of forming contact pedestals and to integrated circuitry employing contact pedestals. The invention also relates to methods of forming a storage node of a capacitor.
BACKGROUND OF THE INVENTION
As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. The principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors.
Conventional stacked capacitor DRAM arrays utilize either a buried bit line or a non-buried bit line construction. With buried bit line constructions, bit lines are provided in close vertical proximity to the bit line contacts of the memory cell field effect transistors (FETs), with the cell capacitors being formed horizontally over the top of the wordlines and bit lines. With non-buried bit line constructions, deep vertical contacts are made through a thick insulating layer to the cell FETs, with the capacitor constructions being provided over the word lines and beneath the bit lines. Such non-buried bit line constructions are also referred to as “capacitor-under-bit line” or “bit line-over-capacitor” constructions.
In DRAM and other integrated circuitry, ohmic electrical contact is typically made relative to an electrically conductive diffusion region in a semiconductor substrate between a pair of conductive lines provided over the substrate. In some instances, contact plugs or pedestals are utilized to facilitate making electrical connection to the substrate, and contend with adverse vertical topography. Such can provide the advantage of producing a larger targeting area for a subsequent conductive line contact to the diffusion region through the pedestal. My earlier U.S. Pat. Nos. 5,338,700; 5,340,763; 5,362,666; and 5,401,681 are hereby incorporated by reference into this disclosure.
REFERENCES:
patent: 4855801 (1989-08-01), Kuesters
patent: 4898841 (1990-02-01), Ho
patent: 4994893 (1991-02-01), Ozaki et al.
patent: 5010039 (1991-04-01), Ku et al.
patent: 5045899 (1991-09-01), Arimoto
patent: 5047817 (1991-09-01), Wakamiya et al.
patent: 5068711 (1991-11-01), Mise
patent: 5134086 (1992-07-01), Ahn
patent: 5166090 (1992-11-01), Kim et al.
patent: 5170243 (1992-12-01), Dhong et al.
patent: 5192703 (1993-03-01), Lee et al.
patent: 5206183 (1993-04-01), Dennison
patent: 5227322 (1993-07-01), Ko et al.
patent: 5231296 (1993-07-01), Rodder
patent: 5243220 (1993-09-01), Shibata et al.
patent: 5266514 (1993-11-01), Tuan et al.
patent: 5292678 (1994-03-01), Dhong et al.
patent: 5330934 (1994-07-01), Shibata et al.
patent: 5338700 (1994-08-01), Dennison et al.
patent: 5340763 (1994-08-01), Dennison
patent: 5340765 (1994-08-01), Dennison et al.
patent: 5354712 (1994-10-01), Ho et al.
patent: 5362666 (1994-11-01), Dennison
patent: 5401681 (1995-03-01), Dennison
patent: 5451539 (1995-09-01), Ryou
patent: 5464787 (1995-11-01), Ryou
patent: 5468671 (1995-11-01), Ryou
patent: 5492850 (1996-02-01), Ryou
patent: 5538592 (1996-07-01), Chen et al.
patent: 5556802 (1996-09-01), Bakeman, Jr. et al.
patent: 5597756 (1997-01-01), Fazan et al.
patent: 5604147 (1997-02-01), Fischer et al.
patent: 5605857 (1997-02-01), Jost et al.
patent: 5608247 (1997-03-01), Brown
patent: 5629539 (1997-05-01), Aoki et al.
patent: 5677557 (1997-10-01), Wuu et al.
patent: 5686747 (1997-11-01), Jost et al.
patent: 5700731 (1997-12-01), Lin et al.
patent: 5702990 (1997-12-01), Jost et al.
patent: 5705838 (1998-01-01), Jost et al.
patent: 5789304 (1998-08-01), Fischer et al.
patent: 5801079 (1998-09-01), Takaishi
patent: 5821140 (1998-10-01), Jost et al.
patent: 5900660 (1999-04-01), Jost et al.
patent: 0-540930 (1993-05-01), None
patent: 0 696 052 (1996-02-01), None
patent: 62-286270 (1986-06-01), None
patent: 63-133565 (1986-11-01), None
patent: 62-232821 (1987-10-01), None
patent: 1-100960 (1987-10-01), None
patent: 1-215060 (1988-02-01), None
Ahn et al, :Micro Villus Patterning (MVP) Technology for 256Mb DRAM Stack Cell, IEEE 1992, pp. 12-13.
Ema et al., “3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs”, IEEE 1988, pp. 592-595.
Hayashide et al., “Fabrication of Storage Capacitance-Enhanced Capacitors with a Rough Electrode”, Extended Abstracts of the 22nd Conference on Solid State Devices and Materials, Sendai, 1990, pp. 869-872.
Iguchi et al., “A Novel DRAM Memory Cell with Inclined-Channel Transistor And Ring-Like Structure Produced Through Self-Aligned Storage Contact Process”, Symposium on VLSI Technologies, 1991.
Inoue et al., “A Spread Stacked Capacitor (SSC) Cell for 64MBit DRAMs”, IEEE 1989, pp. 31-34.
Itoh et al., “Two Step Deposited Rugged Surface (TDRS) Storagenode And Self Aligned Bitline-Contact Cellplate (SABPEC) for 64MbDRAM STC Cell”, Symposium on VLSI Technologies, date unknown.
Kaga et al., “Crown-Shaped Stacked-Capacitor Cell For 1.5-V Operation 64-Mb DRAMs”, IEEE, Feb. 1991.
Kawamoto et al., “A 1.28 Bit-Line Shielded Memory Cell Technology For 64MB DRAMs”, Symposium on VLSI Technology 1990.
Kusters, et al., “A Stacked Capacitor Cell With A Fully Self-Aligned Contact Process For High Density Random Access Memories”, J. Electrochem. Soc. vol. 139, No. 8, Aug. 1992.
Ozaki et al., “A Fence Stacked Capacitor (FSC) Cell For 256 Mbit DRAMs”.
Shibata et al., “A Novel Zero-Overlap/Enclosure Metal Interconnection Technology”, VMIC Conference 1990, pp. 15-21.
Temmler, “Multilayer Vertical Stacked Capacitors (MVSTC) For 64Mbit and 256 Mbit DRAMs”, date unknown.
Wakamiya et al., “Novel Stacked Capacitor Cell For 64 Mb DRAM”, date unknown.
“Stacked Capacitor DRAM Cell With Vertical Fins (VF-STC)”, IBM Technical Disclosure Bulletin, vol. 33, No. 2, Jul. 1990.
Brophy Jamie L.
Jr. Carl Whitehead
Micro)n Technology, Inc.
Wells, St. John, Roberts Gregory & Matkin P.S.
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