Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-01-22
2001-12-04
Ray, Gopal C. (Department: 2181)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S010000
Reexamination Certificate
active
06327670
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a duplex controller having a write through update bus connecting an active processor circuit and a redundant standby processor circuit for updating the memory of the standby processing circuit when the memory of the active processing circuit is updated.
2. Description of the Related Art
The fault tolerance of a data processing system relates to the ability of the system to continue performing a task after the occurrence of a fault. One of the ways in which systems achieve increased fault tolerance is by incorporating hardware redundancy. Fault tolerance is extremely important in systems which require high reliability such as aircraft control systems, life-support systems, and other industrial control systems. Redundant or duplicative data processors are used in controllers to increase the availability and reliability of the systems in which they are used.
Controllers which have standby processors may comprise many different configurations. For example, some systems include a quasi-duplicative arrangement in that only some of the parts of the circuit are duplicated. In other configurations in which high reliability is extremely critical, the entire circuits are duplicated. However, even in those systems in which an entire hardware circuit is duplicated, some amount of time is required to switch from using the active controller to the standby controller. For example, if the standby controller lacks the state information of the failed active side, the system must re-initialize to allow the standby side, which is now the active side, to recreate or reproduce a useful state, which is time consuming. This associated delay deteriorates the availability of the overall device which may include many of these redundant circuits. One way to avoid this delay is to have the standby controller perform ongoing tasks simultaneously with the active controller. In this way, the standby processor is always in the same state as the active processor and can assume control immediately. However, this arrangement consumes approximately double the power of a single circuit and may therefore be prohibitive in many systems in which numerous components have a redundant standby device. Also, these types of circuits normally require additional complex circuitry for ensuring that the active and standby circuits are performing the same operations simultaneously and producing the same results.
SUMMARY OF THE INVENTION
The present invention provides a duplex controller with a pair of redundant processor circuit members connected by an update bus. The duplex controller is designed for use in a system which requires high reliability. To that end, each of the redundant processor circuit members is individually capable of performing the tasks of the duplex controller. Thus, the controller remains operable when one of the processor circuit members fails. In addition, the update bus is connected such that when the active member executes a write command, the write command is also effected at the standby circuit. The memory of the standby circuit is maintained so that when control of the duplex controller is transferred to the standby circuit, the memory of the standby circuit is instantaneously ready with up to date information, thereby limiting the delay time required for switching control to the standby circuit and maximizing the availability of the overall system.
Each processor circuit member includes a processor, memory, and an update bus interface. At any given time, one of the processor circuit members is in an active state. The active member executes applications and software programs to perform tasks. The second member is in a standby state and stands by ready to become active, if needed. The update bus connects the pair of processor circuits so that each member has access to the other member's memory. In a normal update mode of the duplex controller, all writes to the memory of the active processor are transmitted via the update bus to the standby processor's memory, thereby keeping the standby processor's memory and registers up to date, so that the standby member can immediately assume control when required.
The connection between the pair of processors may be disabled, loosely coupled, or tightly coupled. In loosely coupled operation, either memory may be accessed by the other of the active and standby members. In tightly coupled operation, all writes to the active member memory are automatically mapped to both the active and standby members, with no intervention from software.
The update bus may be operated in the following modes:
Normal Mode—In this mode, the two members are tightly coupled. All read operations are directed to the local side only. However, each write operation is performed at the local (active) side with a matching write to the mate (standby);
Forced Local—This mode is used when it is desired that only the local memory space is to be accessed, without disturbing devices on the mate side;
Forced Mate—This mode is used when it is desired that only the mate memory space be accessed, without disturbing the devices on the local side; and
Forced Both—This mode is very similar to Normal Mode except that both local and mate memories are accessed during both read and write operations. This mode may be used when it is necessary to trigger the same strobe point on both the local and mate sides.
As stated above, the write through update bus according to the present invention is designed to limit the amount of time required to switch control from the active processing circuit to the standby processing circuit. Therefore, the circuit operates most efficiently if it is operated in Normal Mode as often as possible. This ensures that the standby processing circuit is always ready to assume control of the duplex controller with up-to-date memory.
REFERENCES:
patent: 3767863 (1973-10-01), Borbas et al.
patent: 5761705 (1998-06-01), DeKoning et al.
patent: 5778206 (1998-07-01), Pain et al.
patent: 6073251 (2000-06-01), Jewett et al.
Hellenthal Klaas
McTee Ricky Raymond
Reneker Douglas Alan
Woods Gordon Douglas
Yu Wai-Ching
Lucent Technologies - Inc.
Ray Gopal C.
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