Dynamic random access memory

Details Dynamic random access memory Dynamic random access memory

2000-10-16

2001-10-23

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S230060

Reexamination Certificate

active

06307796

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) and, more particularly, to stress applying means for applying voltage stress to word line groups more acceleratedly than a normal use at the time of screening defectiveness in a wafer state.
2. Description of the Related Art
A screening is generally performed to expose latent defects in semiconductor devices and remove from finished batches those devices having defects. This screening process prevents defect-free devices from being adversely affected by defective devices and ensures the reliability of the finished semiconductor devices when they are put on the market. As one screening method, a burn-in capable of accelerating an electric field and a temperature at the same time is frequently employed. In this burn-in, semiconductor devices are operated using a voltage higher than the actual working voltage and a temperature higher than the actual working temperature, and voltage stress is applied to the semiconductor devices for a short period of time longer than the initial failure period under actual working conditions. The semiconductor devices are then screened and those which are considered likely to malfunction in initial operation are removed. This type of screening is an efficient method of removing defective devices, thereby enhancing the reliability of finished semiconductor devices.
In recent DRAMs, a potential (for example, approximately 1.5×Vcc) boosted when a transfer gate (hereinafter referred to as cell transistor) of selected memory cell is applied to a gate oxide film of the memory cell transistor. Even though the gate oxide film is thick, a strong electric field is applied thereto and thus the reliability of the DRAMs may be lowered. It is thus necessary to actively screen cell transistors having gates to which a boosted potential is applied when the burn-in of DRAMs is performed.
To screen the memory cells when the burn-in of the DRAMs is performed, a method of scanning an address so as to sequentially access word lines connected to the gates of the cell transistors was conventionally used. In this method, voltage stress is applied to the cell transistors less frequently than to transistors of a peripheral circuit and a time period for which the greatest electric field is actually applied to the cell transistors is short; accordingly, a long time is needed for the burn-in of DRAMs.
In order to eliminate the above drawback wherein the voltage stress is applied to the cell transistors less frequently, one of the inventors of the present invention proposed a semiconductor memory capable of improving in efficiency with which voltage stress is applied to cell transistors, as disclosed in Published Unexamined Japanese Patent Application (kokai) No.
3-35491
which corresponds to U.S. Pat. application Ser. No. 07/544,614. The semiconductor memory is so formed that voltage stress can be applied to all word lines or word lines more than those selected in a normal operation mode when a defective cell transistor is screened.
If the above proposal is applied to a DRAM, defective cell transistors can considerably be reduced and 1M or 4M DRAMs having bit defects can be decreased at high speed by the screening. Therefore, the screening can be greatly improved in efficiency.
It is desirable to materialize a means for applying voltage stress to all word lines or word lines more than those selected in the normal operation mode when a operation power is supplied to the DRAMs.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation and its object is to provide a dynamic random access memory (DRAM) capable of greatly improving the efficiency of a screening which is performed when operation power is supplied to the DRAM.
To attain the above object, a dynamic random access memory according to the present invention comprises: a plurality of dynamic memory cells arranged in rows and columns; a word line connected to the memory cells on the same row; a bit line connected to the memory cells on the same column; a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal; a word line driving voltage source; a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and word line, for driving the word line in response to an output signal of the word line selecting circuit; and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.
According to an aspect of the present invention, when operation power is supplied to the dynamic random access memory to perform a screening, voltage stress can be applied to all word lines or word lines more than selected in the normal operation mode through the word line driving circuit in response to the voltage stress test control signal. It is thus possible to screen cell transistors with high efficiency.
If the cell transistors are N-channel type MOS transistors, a P-channel type MOS transistor is used as a word line driving transistor connected between the word line driving voltage source and word line, and the gate of the P-channel type MOS transistor is fixed to the ground potential to stabilize the gate node. It is thus possible to stably apply the voltage stress to the word line through the P-channel type MOS transistor.
The control circuit has a relatively simple arrangement, and the DRAM chip need not increase in the area for the control circuit.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.


REFERENCES:
patent: 4344005 (1982-08-01), Stewart
patent: 4651029 (1987-03-01), Oritani
patent: 4651304 (1987-03-01), Takata
patent: 4654849 (1987-03-01), White, Jr. et al.
patent: 4751679 (1988-06-01), Dehganpour
patent: 4782247 (1988-11-01), Yoshida
patent: 4873669 (1989-10-01), Furutani et al.
patent: 4969124 (1990-11-01), Luich
patent: 4999813 (1991-03-01), Ohtsuka et al.
patent: 5113374 (1992-05-01), Matsui
patent: 5157629 (1992-10-01), Sato et al.
patent: 5233610 (1993-08-01), Nakayama et al.
patent: 5245583 (1993-09-01), Li
patent: 5255229 (1993-10-01), Tanaka et al.
patent: 5258954 (1993-11-01), Furuyama
patent: 5265057 (1993-11-01), Furuyama et al.
patent: 5276647 (1994-01-01), Matsui et al.
patent: 5282167 (1994-01-01), Tanaka et al.
patent: 5298433 (1994-03-01), Furuyama
patent: 5307315 (1994-04-01), Oowaki et al.
patent: 5335205 (1994-08-01), Ogihara
patent: 62-20198 (1985-07-01), None
patent: 62-150600 (1985-12-01), None
patent: 63-133391 (1986-11-01), None
patent: 63-292485 (1988-11-01), None
patent: 64-52300 (1989-02-01), None

Affiliated with

Also associated with

Rating

Dynamic random access memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic random access memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic random access memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2560483