Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1997-11-13
2001-02-13
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S702000
Reexamination Certificate
active
06187671
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to a contact structure of a semiconductor device for use in miniaturized semiconductor devices such as submicron devices, as well as a semiconductor device that uses such a contact structure. Further, the present invention relates to a contact structure for use in semiconductor integrated circuits having a multilayer interconnection structure and a semiconductor integrated circuit having such a contact structure.
With the development of photolithography, miniaturization of semiconductor devices is continuing. Currently, semiconductor devices having a submicron pattern size are produced successfully by using an advanced photolithographic system. Further, recent semiconductor integrated circuits of a large integration density and hence including large number of semiconductor devices therein, are increasingly using a multilayer interconnection structure in which wiring or interconnection patterns are provided in plural layers with an interlayer insulation structure intervening therebetween.
When producing such submicron semiconductor devices in the form of integrated circuit, it is necessary to provide minute contact holes of submicron size on an insulation layer having a stepped surface.
FIGS. 1A and 1B
show a typical example of forming such a minute contact hole in an insulation layer having a stepped surface.
Referring to
FIG. 1A
showing a part of a semiconductor integrated circuit, it will be noted that a field oxide film
2
is provided on a semiconductor substrate
1
so as to define an active region that includes a diffusion region
3
. On the field oxide film
2
, it will be noted that a conductor pattern
4
having a submicron width is provided, wherein the conductor pattern
4
may be a gate pattern of a MOS transistor. In this case, the conductor pattern
4
extends in the direction generally perpendicularly to the sheet of the drawing and forms a gate electrode in an active region not illustrated in FIG.
1
A.
The conductor pattern
4
is covered by an insulation film
5
that may include a silicon oxide film deposited on the substrate
1
by a CVD process so as to cover the diffusion region
3
as well as the field oxide film
2
including the conductor pattern, wherein a planarization layer of BPSG or the like, may be provided further on the silicon oxide film to form the foregoing insulation film
5
.
In the state of
FIG. 1A
, a photoresist
6
is applied on the insulation film
5
, wherein the photoresist
6
includes openings
6
A and
6
B formed by a photolithographic process that includes exposure and development of the photoresist
6
, such that the surface of the insulation film
5
is exposed at the openings
6
A and
6
B.
Next, in the step of
FIG. 1B
, a reactive ion etching process is applied to the structure of
FIG. 1A
while using the photoresist
6
as a mask, to form contact holes
5
A and
5
B respectively in correspondence to the openings
6
A and
6
B of FIG.
1
A. The contact holes
5
A and
5
B thus formed expose the diffusion region
3
and the conductor pattern
4
respectively, and the structure of
FIG. 1B
is ready for formation of a wiring pattern thereon for interconnecting various parts of the semiconductor devices formed on the substrate
1
.
In such a process, it should be noted that, because of the existence of stepped structure on the part of the insulation layer
5
covering the conductor pattern
4
, which in turn is located on the field oxide film
2
, there is a tendency that the photoresist
6
has a reduced thickness t
2
in the region immediately above the conductor pattern
4
where the opening
6
B is formed, as compared with a thickness t
1
for the part of the photoresist
6
located above the diffusion region
3
on which the opening
6
A is formed. Further, associated with the reduced thickness of the photoresist
6
on the part located above the conductor pattern
4
, the insulation film
5
also has a reduced thickness in the part covering the conductor pattern
4
as compared with the part covering the diffusion region
3
. Such a variation in the thickness of the insulation film
5
may reach as much as twice the minimum thickness of the film
5
.
In such a case, the etching of the layer
5
immediately reaches the conductor pattern in the opening
6
B while in the state that the etching of the layer
5
is still in progress in the opening
6
A. In such a case, chemical species produced as a result of interaction between the plasma used in the reactive ion etching process and the conductor pattern
4
, attack the side wall of the contact hole
5
B, and the size of the contact hole
5
B is substantially increased as a result as compared with a nominal size indicated in
FIG. 1B
by a broken line. Further, the opening
6
B of the resist
6
may increase the size thereof as indicated in
FIG. 1A
by arrows as a result of continuous application of plasma to the photoresist
6
in correspondence to the part where the thickness of the resist
6
is reduced. It should be noted that, while the photoresist
6
has a large resistance against etching as compared with the insulation film
5
, such a resistance is by no means infinite.
As a result, the conventional process and the contact structure produced as a result of such a process have suffered from the problem of uncontrolled increase in the size of the contact hole, known as CD (critical dimension) loss. Further, such a contact hole that experienced the problem of CD loss generally shows an irregular shape as indicated in FIG.
2
. It should be noted that such an irregular shape occurs as a result of attack of the contact hole side wall by the species produced as a result of reaction between the plasma and the conductor such as the conductor pattern
4
.
When an electric contact is formed at such an irregular contact hole, there tends to occur the problem of electromigration in which the electrons concentrated to sharp points in the contact hole induce a displacement of the metal atoms filling the contact hole, leaving behind a void. Similarly, there occurs the problem of stress migration. Thereby, the electrical contact becomes unreliable and the life-time of the contact is reduced significantly.
Further, such an unwanted and uncontrolled increase in the size of the contact hole can be detrimental to minute semiconductor devices such as submicron devices in which the conductor pattern
4
has a width smaller than one micron.
In addition, the existence of stepped structure on the surface of a layer in which a submicron contact hole is to be formed, raises the well known problem of insufficient focal depth of the optical system that is used in a high resolution photolithography. It should be noted that the high resolution optical exposure systems for use in high-resolution, submicron photolithography generally have an optical system of large numerical aperture for increased resolution, while the optical system of such a large numerical aperture can provide only a very limited focal depth. Thus, simultaneous exposure of contact holes at two different levels is extremely difficult as long as such a high resolution optical exposure system is used.
In relation to the formation of minute, submicron contact holes, various proposals are made so far.
For example, the Japanese Laid-open Patent Publication 4-125925 describes a process in which a minute contact hole is formed in a larger, but shallower depression formed in an insulation film.
FIGS. 3A-3E
show the process proposed in the foregoing reference.
Referring to
FIG. 3
, a photoresist
12
is provided on an insulation film
11
covering the surface of a Si substrate
10
in the step of
FIG. 3A
, wherein the photoresist
12
is formed with an opening
12
A as a result of a photolithographic patterning process. The insulation film
11
may include a CVD-deposited silicon oxide film and a PSG layer formed thereon.
Next, in a step of
FIG. 3B
, an RIE process is applied to the insulation film
11
while using
Bowers Charles
Cooper & Dunham LLP
Kilday Lisa
Ricoh & Company, Ltd.
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