Semiconductor memory device and method of testing the same

Details Semiconductor memory device and method of testing the same Semiconductor memory device and method of testing the same

1992-04-23

1994-04-19

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

365200, 365207, G11C 700

Patent

active

053052617

ABSTRACT:
A sense.multidot.input/output gate includes MOS transistors which are provided for each bit line pair and have their gates and drains cross-coupled together, separating transistors arranged between the gates and the drains of the MOS transistors, and column selecting gates connecting the drains of the MOS transistors to internal data transmitting lines. The semiconductor memory device further includes a load circuit which precharges the internal data transmitting lines to a predetermined potential in a test mode, and a line test circuit which determines existence and nonexistence of a defective memory cell based on the potentials of the internal data transmitting lines. In the data reading operation, the column selecting gates become conductive while the separating transistors are in OFF state, and the potential of the internal data transmitting line changes by virtue of the discharge through one of the cross-coupled MOS transistors. In this construction, the sense amplifier is used also as the read gate. Therefore, high-speed reading of data is allowed, and tests for many memory cells in up to one row can be simultaneously performed. Accordingly, a test time is reduced in a highly integrated semiconductor memory device.

REFERENCES:
patent: 4972372 (1990-11-01), Ueno
patent: 5088063 (1992-02-01), Matsuda et al.
patent: 5184326 (1993-02-01), Hoffmann et al.
Feb. 1989 IEEE Solid-State Circuits Conference, Technical Paper Seiten 244,245.
"A 1.5V Circuit Technology for 64Mb DRAMs", by Y. Nakagome et al, 1990 Symposium on VLSI Circuits, pp. 17-18.
"A 45ns 64Mb DRAM with a Merged Match-line Test Architecture", by Shigeru Mori et al, 1991 IEEE International Solid-State Circuits Conference, pp. 110-111.

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