Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-11-10
2001-12-11
Wojciechowicz, Edward (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S230000, C438S265000, C438S299000, C438S303000, C438S514000, C257S327000, C257S335000, C257S336000
Reexamination Certificate
active
06329225
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of integrated circuits, and more particularly to tight pitch gate devices with enlarged contact areas for deep source and drain terminals and a method for forming the same.
BACKGROUND OF THE INVENTION
Modern electronic equipment such as televisions, telephones, radios and computers are generally constructed of solid state devices. Solid state devices are preferred in electronic equipment because they are extremely small and relatively inexpensive. Additionally, solid state devices are very reliable because they have no moving parts, but are based on the movement of charge carriers.
Solid state devices may be transistors, capacitors, resistors, and other semiconductor devices. Typically, such devices are formed in and on a substrate and are interconnected to form an integrated circuit. One type of transistor is the metal oxide semiconductor field effect transistor (MOSFET) in which current flows through a narrow conductive channel between a source and drain and is modulated by an electric field applied at the gate electrode. In tight pitch gate applications such as memory arrays, for example, MOSFETs may be packed within 2,000-3,000 angstroms of one another.
A MOSFET is typically fabricated by forming the gate electrode outwardly of a substrate. Dopants are implanted and diffused into the substrate on either side of the gate electrode to form the source and drain as well as pockets and extensions for the source and drain. Contacts connect each of the gate electrode, source, and drain to other components of the integrated circuit.
To minimize short channel effects that degrade device performance, the source and drain are spaced apart from the conductive channel underlying the gate electrode. This is generally accomplished during fabrication by enlarging the sidewall insulator formed along the gate electrode to act as a spacer and prevent source and drain dopant implant in the substrate next to the gate. For tight pitch applications having small device size, however, the enlarged sidewall spacer takes up a large fraction of the area between the adjacent gate electrodes. As a result, contact areas for the source and drains are reduced and device yield is decreased.
SUMMARY OF THE INVENTION
In accordance with the present invention, tight pitch gate devices with enlarged contact areas for source and drain terminals and method are provided that substantially eliminate or reduce disadvantages and problems associated with previously developed systems and methods. In particular, the present invention provides implant sidewalls that limit dopant implant area during source and drain formation and that are later removed to enlarge contact areas for the source and drain.
In one embodiment of the present invention, an enlarged contact area is formed for a gate device by providing a substrate having thereon at least one gate electrode. An implant sidewall is formed outwardly from the gate electrode and defines an implant area in the substrate. A terminal is formed for the gate electrode by implanting dopants into the implant area in the substrate. The implant sidewall is removed and an insulative sidewall is formed outwardly from the gate electrode. The insulative sidewall has a thickness less than that of the implant sidewall to define an enlarged contact area for the terminal.
Technical advantages of the present invention include providing enlarged contact areas between gate devices in memory arrays and other tight pitch applications. In particular, the contact area for the terminal is enlarged without adverse effect upon terminal spacing from the gate electrodes. This is accomplished by a removable implant sidewall that is used to limit dopant implant area during source and drain formation and thereafter removed to leave a contact area larger than the implant area. The enlarged contact area allows for better connections between the source and drains of the gate devices and other components of the integrated circuit. Accordingly, device yield is increased.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.
REFERENCES:
patent: 6144065 (2000-11-01), Kinzer
“Raised Source/Drain MOSFET with Dual Sidewall Spacers,” by Mark Rodder, D. Yeakley, IEEE Electron Device Letters, vol. 12, No. 3, Mar. 1991.
Brady W. James
Hoel Carlton H.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Wojciechowicz Edward
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